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I2C Clock not generated by master....

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Am using DW_apb_i2c IP - Standard mode. I can able to see start bit but after start bit both SDA and SCL is held low. What could be the problem.Here, Processor is the master and I2C device is the Slave.
 

Possibly no pullup. Possibly an issue with a level translator if one is on the board. While a slave could pull SCL low to indicate "busy", that really seems unlikely on the start bit.
 

5K pull up is connected as per the spec. Actually am trying to upgrade the Master from cortexr5 to cortexr8. With the cortextr5 FW code i can able to see the the expected behavior. But with the R8 FW code i face this problem and am using the same configuration for both case.
 

Hi,

Please show your code, schematic and wiring, maybe scope pictures...

Else it´s just guessing.

Klaus
 

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