Sampling Rate and PID loop timing in a Tyrister based charger

I am trying to do a Phase control Battery charger. Plans to Do Phase control to maintain and apply voltage to battery with a monitor and limit for current.
PIC16 ADC monitors voltage and current. PID algorithm derives the required phase angle for voltage, if current exceeds in the lower voltages, needs to reduce voltage and keeps the charging current in limit.
As for now My ADC reads voltage and current being read in 5ms intervals unto 16 samples and taking average. So my Feed back response is ready every 80ms. which is adjustable off course!
What will be the ideal sampling rate and PID loop frequency in a application like this? My voltage feed back passes through a low pass filter which has around below 5 ms lag.
Thanks

Hi,

If I had to do it, I'd surely use 2x mains_frequency. Synchronized to mains frequency.

Running the PID loop faster will have no effect, because the thristor can only be activated once per halfwave.
There is no nee to run the PID loop slower, because, every microcontroller should have enough processing power to calculate the values every halfwave.
If you choose a slower PID rate, this just may decrease stability.
For a regulation loop: the faster the response, the easier it is to keep it stable.

I see only one benefit in a slower PID frequency: This is when you exactly calculate it 1x per fullwave. The benefit is that the negative and positive phase angle will be the same...resulting in equal load in both halfwaves.

*****
Your values:
* 16 values x 5ms. Difficult. For me a "no go" if you are not synchronized to mains frequency. Imagine: in worst case you do a conversion at zero cross and the other close to the mains peak.
--> I recommend to do the conversion synchronized to mains frequency at zero cross. Thus the measurement is not that influenced by mains current and phase control angle.

The other useful method is to do the measurement in "oversampling style" with an exact integer multiple of mains frequency: let's say 32 times per full wave and calculate the average.
In either case I recommend to suppress overtones with an at least second order LPF, to get stable measurement results.

* 5ms time lag LPF:
Only useful if sampling is in sync with mains frequency.
If not in sync with mains frequency you need a much higher time lag, because then you need to suppress not only the overtones, but also the fundamental. The ADC input then should look like DC. Else you should expect very low alias frequency fluctuations.

*****
My experience: I've designed a fast and precise SCR controlled current source 400V/250A. Short circuit proof, with adaptive (to load impedance) loop stabilization. Optimized PI loop.

Klaus

KlausST said:

I see only one benefit in a slower PID frequency: This is when you exactly calculate it 1x per fullwave. The benefit is that the negative and positive phase angle will be the same...resulting in equal load in both halfwaves.

Your values:
* 16 values x 5ms. Difficult. For me a "no go" if you are not synchronized to mains frequency. Imagine: in worst case you do a conversion at zero cross and the other close to the mains peak.
--> I recommend to do the conversion synchronized to mains frequency at zero cross. Thus the measurement is not that influenced by mains current and phase control angle.

The other useful method is to do the measurement in "oversampling style" with an exact integer multiple of mains frequency: let's say 32 times per full wave and calculate the average.
In either case I recommend to suppress overtones with an at least second order LPF, to get stable measurement results.

Klaus

Click to expand...

Thanks for the valuable input. Let me first Sync the ADC reading Triggering Timer with Zero cross detection Pulse and then Read 32 samples 625uS apart. That gives a Feed back every cycle and we can update PID every cycle. In that case my LP filter lag also can be accommodated without any problem - I believe!
Thanks

I agree that synchronizing to mains frequency is beneficial.

As to sample rate I'd suggest over-sampling is beneficial for overall performance.

Note that your modulator can in-fact response faster than the switching period. Consider a modulator based on a counter which mimics an analog ramp signal - the eamp can update more than once a cycle and the modulator can be designed to change SCR states as soon as it sees the eamp output 'cross' the counter ramp (just like an analog system). I'm not going to say this gets a huge advantage, but it's also often not hard to implement things this way.


As to the filters I'll note this: There is no distinction between the filters and the PID. The PID is a type of filter (one pole, two zeros) and the LPF is simply another pole (or more) in series with the PID.

So you need to take care to get the analog signals into the digital domain reliably, which may require analog filtering (below the nyquist frequency of your sample rate), but once in the digital domain it makes no difference whether you put low pass filters in front of or behind your PID. And any decision to add filtering should be based on a conscious choice to add poles to your overall loop transfer function.

I remember in the past thinking it obvious that you would need to give your error amplifier a clean signal by filtering it first - but the eamp IS a filter. So that distinction is silly (and dangerous since poles in the wrong place can set up instability).

Note that a PID with two additional poles is a standard Type III compensator. A PI plus another pole is a TypeII compensator and an integrator alone is TypeI.

One last thing: PSIM, Matlab/Simulink etc are really good at simulating this stuff. The free version of PSIM should be enough to help you model this system.