golohoyeah
Junior Member level 2
I am testing a PLL which I designed with VCO oscillates at around 400MHz.
I find the lock on time is much slow than that what I simulated from around 150us to several seconds,
and what's more, after the PLL lock to a desired frequency 400MHz, it will stay there for around 10 seconds, and move out the lock to much higher frequency, and stay that frequency forever.
I am wondering what is the possibilities for such result to happen, I am suspecting the supply noise, and driving it with an external source, seems the jitter perform better than before, but the locking issue still there.
I am out of idea now, hope someone can give some hints or suggestion.
best regards,
golohoyeah
I find the lock on time is much slow than that what I simulated from around 150us to several seconds,
and what's more, after the PLL lock to a desired frequency 400MHz, it will stay there for around 10 seconds, and move out the lock to much higher frequency, and stay that frequency forever.
I am wondering what is the possibilities for such result to happen, I am suspecting the supply noise, and driving it with an external source, seems the jitter perform better than before, but the locking issue still there.
I am out of idea now, hope someone can give some hints or suggestion.
best regards,
golohoyeah