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help with function overloading- VHDL

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wtr

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Hello all,

I've scanned the forums and found this thread https://www.edaboard.com/showthread...ggregate&highlight=vhdl+overloading+functions where #4 sort of touches on what I want to do.

Using VHDL subset = 2008

Code VHDL - [expand]
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subtype nibble_t is std_logic_vector(3 downto 0);
subtype byte_t is std_logic_vector(7 downto 0);
subtype word_t is std_logic_vector(15 downto 0);
-- ******
function slv_2_wordtype (word : std_logic_vector) return nibble_t;
function slv_2_wordtype (word : std_logic_vector) return byte_t; -- like I say later - second iteration I apply a range to slv (still get erro)
-- @@@ Vivado is giving me the following errors
-- @@@ "Error: A homograph of slv_2_wordtype is already declared in this region"
--...
--******
function wordtype_2_slv(word : nibble_t) return std_logic_vector;
--...
--******
 
    function slv_2_wordtype(word : std_logic_vector) return nibble_t is
        variable var : nibble_t;
    begin
        var := word;
        return var;
    end function;
-- In this instance I tried to constrain range however still get the same error
    function slv_2_wordtype(word : std_logic_vector(byte_t'range)) return byte_t is
        variable var : byte_t;
    begin
        var := word;
        return var;
    end function;


You may be asking why I'm doing this?

I've got instances where the entity may have byte_t type, and it freaks out when I feed in a slv even though the dimensions are the same.

I know I could have bespoke names but I want to used overloading, so I can apply it to any instance where I need to convert from special word defined dimension to a slv.

Regards,
Wes
 
Last edited:

Vivado is correct.
In VHDL 2008 and previous, you cannot get the subtype from the return of a function. So from the callers POV, both functions return a SLV and wont know which function to call.
VHDL 2018 will allow the compiler/user to know the subtype of the return type of a function, so I assume will allow function overloading based on subtype (but this is currently not possible)

VHDL 2008 LRM said:
Two subprograms are said to have the same parameter and result type profile if and only if both have
the same parameter type profile, and if either both are functions with the same result base type or neither of
the two is a function.
Click to expand...

So different subtypes for the return object does not give two distinct functions.

Im not quite sure what your functions actually do though - because subtypes are the same type as their base type, so assignments between them are legal without any form of conversion:

Code VHDL - [expand]
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signal byte : byte_t;
signal msb, lsb : nibble_t;
 
byte <= msb & lsb;  -- base type is SLV so no type conversion is needed.


- - - Updated - - -

On a side note - VHDL 2008 added the 'subtype attribute for all signals, and the 'element attribute for arrays. So for more complicated types, it means less typing.

Code VHDL - [expand]
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type axis_if_t is record
    tid       : std_logic_vector(7 downto 0);
    tdata     : std_logic_vector;
    tuser     : std_logic_vector;
    tdest     : std_logic_vector;
    tkeep     : std_logic_vector;
    tstrb     : std_logic_vector;
    tlast     : std_logic;
  end record axis_if_t;
 
.....
 
entity some_axis_entity is
  port (
    axis_ip : in axis_if_t;  -- note size determined by connection
.....
 
signal some_internal_axis : axis_ip'subtype; -- match dimensions of the input
 

I've done assignments and not had any problems, but I got a linting warning earlier where I had a word_type assigned to slv.

I guess I may have mis-interpreted the error since I can't replicate it. Likewise I probably misspelled something and that was the actual warning.

- - - Updated - - -

Thanks for the info I'm going to make use of the 'subtype -somewhere-, even if one could easily use "axis_if_t" (which makes code less copy pasta friendly)
 

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