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[SOLVED] Unpacked array in SV is treated as packed array during instantiation

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swabhi812

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Hey RTL experts,

I have an interesting error in my RTL and I would like to take your expert opinion in understanding the same.

Here is the error:
Code:
E-  : <module file name>(<line number>) :
    '2'b00': Type mismatch - no implicit conversion exists to convert the value of the expression of type '[1:0] unsigned logic' into the type required by the context ' logic [1:0]'.

This is what I am doing:


Code Verilog - [expand]
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module Test (
..
..
..
);
 
input logic xyz [1:0];
..
..
endmodule
 
During module instantiation I am tying this input xyz to 2'b00.
 
Test test_inst (
..
..
.xyz (2'b00),
..
..
);



Question: Why is simulation tool treating 2'b00 as packed unsigned array, while I have declared xyz as unpacked array?

Thanks,
Abhishek

- - - Updated - - -

UPDATE: I was able to fix the error, but still want to understand what was wrong with my initial approach.

I was able to get past this violation by using following code during instantiation:


Code Verilog - [expand]
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Test test_inst (
..
..
.xyz ({1'b0,1'b0}),
..
..
);



However, this is inconvenient for a 64 bit bus may be. Do you guys have any insight?

Thanks.
 

2'b00 is treated as a packed array because it IS a packed 2-bit array.
 

2'b00 is treated as a packed array because it IS a packed 2-bit array.


Can you make recommendations about how to code in this scenario, considering 2'b00 being packed.? In case of 64 bit signal as an example.
 

Define your input as
Code:
input logic [1:0] xyz;
instead.
Or if you have a multidimensional array then as
Code:
input logic [63:0][1:0] xyz;
which gives you a packed array of 128 bits with the [0] word located at [63:0] and the [1] word located at [127:64]
 

I have figured out the fix. To make a conversion from packed to unpacked array, we can use streaming operator.

{>>{unpacked_array}} = packed_array;

Thanks.
 

That is one possibility, but not very safe. If you just want to assign a literal number, use an array assignment pattern

Exact:

Code Verilog - [expand]
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.xyz ('{1'b0,1'b0}),



Replication:

Code Verilog - [expand]
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.xyz ('{2{1'b0}}),



Default

Code Verilog - [expand]
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.xyz ('{default:1'b0}),

 

Curious why you said it is not safe to use streaming operator.?
 

I should have said: "not always safe".

You get no warning/error if the number of bits in the packed array is less than the number of bits in the unpacked array. Also, if you are trying assign a particular shape array, there is nothing that tells you your alignment is off.
 

I should have said: "not always safe".

You get no warning/error if the number of bits in the packed array is less than the number of bits in the unpacked array. Also, if you are trying assign a particular shape array, there is nothing that tells you your alignment is off.

Thanks for quick response. Appreciate it.
 

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