swabhi812
Member level 2
Hey RTL experts,
I have an interesting error in my RTL and I would like to take your expert opinion in understanding the same.
Here is the error:
This is what I am doing:
Question: Why is simulation tool treating 2'b00 as packed unsigned array, while I have declared xyz as unpacked array?
Thanks,
Abhishek
- - - Updated - - -
UPDATE: I was able to fix the error, but still want to understand what was wrong with my initial approach.
I was able to get past this violation by using following code during instantiation:
However, this is inconvenient for a 64 bit bus may be. Do you guys have any insight?
Thanks.
I have an interesting error in my RTL and I would like to take your expert opinion in understanding the same.
Here is the error:
Code:
E- : <module file name>(<line number>) :
'2'b00': Type mismatch - no implicit conversion exists to convert the value of the expression of type '[1:0] unsigned logic' into the type required by the context ' logic [1:0]'.
This is what I am doing:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module Test ( .. .. .. ); input logic xyz [1:0]; .. .. endmodule During module instantiation I am tying this input xyz to 2'b00. Test test_inst ( .. .. .xyz (2'b00), .. .. );
Question: Why is simulation tool treating 2'b00 as packed unsigned array, while I have declared xyz as unpacked array?
Thanks,
Abhishek
- - - Updated - - -
UPDATE: I was able to fix the error, but still want to understand what was wrong with my initial approach.
I was able to get past this violation by using following code during instantiation:
Code Verilog - [expand] 1 2 3 4 5 6 7 Test test_inst ( .. .. .xyz ({1'b0,1'b0}), .. .. );
However, this is inconvenient for a 64 bit bus may be. Do you guys have any insight?
Thanks.