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difference between priority case and case

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stanford

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For priority case, if all the conditions are not listed, unlisted case items are don’t cares, and can be optimized away.
For case, if all the conditions are not listed, it will synthesize into a latch.

Is this correct?

Thanks
 

stanford said:
For priority case, if all the conditions are not listed, unlisted case items are don’t cares, and can be optimized away.
For case, if all the conditions are not listed, it will synthesize into a latch.

Is this correct?

Thanks
Click to expand...

I dont think that is true. Priority case will tell simulation and synthesis tools to generate priority encoded logic. However, if no case matches, you will encounter a violation in simulation:

RT Warning: No condition matches in 'priority case' statement.

However, if you use unique case statement, if you do not add a case condition it will not add latch. For example in case of a 3:1 MUX.

Code Verilog - [expand]
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always_comb begin
  unique casez(select) begin
    2'b00 : y = a;
    2'b01 : y = b;
    2'b10 : y = c;
  endcase
end // always_comb
 

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