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How to simulate bidirectional signal in LTSPICE

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flote21

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Hello guys!

I am trying to simulate the next circuit in LTSPICE:

pic1.png

I was expecting to see something like this:

pic2.png

However I got this:

pic3.png

I can only see one pulse and I think that maybe I am doing something wrong in the simulation because I am trying to emule the behavior of a uC outputs with two signal generators...

Thanks in advance.
 

The result looks expectable. You're apparently ignoring that the circuit implements a wired AND rather than OR function.
 

Hi FvM!

Thanks for the clarification. However I need to have both pulses at the output of the trigger-schmitt buffers. For example, if place two 1k resistors at the colector of every BJT you can get this solution. However the pulses are not reaching the desired voltage levels...Any idea?

Thanks in advance.
 

However the pulses are not reaching the desired voltage levels

It's necessary to start with a simpler circuit, which lets you adjust component values and watch how a mosfet responds in the simulator. See what happens with various combinations of volt levels, until you obtain your desired output.
 

Hi BradTheRad,

I have already tested several combination of resistors and as far as I place resistors at the collector of every BJT, I am not able to reach the desired levels of the pulses...So I think that maybe I have to change my design in order to get the desired working...

Thanks anyway!

It's necessary to start with a simpler circuit, which lets you adjust component values and watch how a mosfet responds in the simulator. See what happens with various combinations of volt levels, until you obtain your desired output.
 

1.

It is unclear what is the supply V to your schmitt trigger IC, whether 15 or 24V?
It may affect what is the upper and lower input voltage which is needed to change the output state.

2.

Your right-hand IC has 3 resistors as a divider going to its input. It's unclear what volt levels reach that input.
 

Thanks for the clarification. However I need to have both pulses at the output of the trigger-schmitt buffers. For example, if place two 1k resistors at the colector of every BJT you can get this solution. However the pulses are not reaching the desired voltage levels...Any idea?
I forgot to mention an obvious point. Your first post is very unclear, you neither explain the intended function clearly nor tell which voltage is actually probed in the simulation. It would be also a good idea to post the zipped Ltspice file to allow others to check the circuit details.

Though this lack information, it seems to me that the problem is a simple error of reasoning regarding circuit operation, which I addressed with the keyword wired AND. Your answer suggests that you didn't yet think about the point.

The simple point is: The output node(s) can only swing to high level if both transistors are switched off. This is only the case for 60ms..70 ms. Maybe it's only a problem of inverted logic? A wired AND bidirectional bus must use high as idle level with all drivers switched off.
 

Hi!

The Trigger-Schimitt buffer only switch between 0-1V (digital logic simulation in LTSpice). In a real life they should switch between 0-3.3V and the resistor divider is to reduce the maximum voltage. However it was a mistake, and the right design should be something like this:

pic1.png

Greetings


1.

It is unclear what is the supply V to your schmitt trigger IC, whether 15 or 24V?
It may affect what is the upper and lower input voltage which is needed to change the output state.

2.

Your right-hand IC has 3 resistors as a divider going to its input. It's unclear what volt levels reach that input.
 

In your test setup, both transistors are pulling down the bus in idle state. Respectively no pulse is emitted at t=0. Reconsider the logic operation.

I presume, you have supplemented the 1k resistors as short circuit protection. But they are considerably reducing the logic swing, current limited drivers may be a better idea.
 

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