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Series-parallel Low transconductance OTA

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ICdesignerbeginner

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Hi

I want to design very low transconductance in nA/V. For that I came across one research article suing series parallel combination of NMOS. I can undertsand that using parallel transistors reduces the current by splitting and flowing through ground but what is the purpose of series transistors? Can some one help me in understanding how series transistors are helping in reducing the transconductance. I am attaching the figure of series parallel OTA.

seriesparallelOTA.png
 

Yes its in the circuit and I can understand that parallel transistors are helping in reducing the transconductance but I think theres no need of series transistors how they are reducing transconductance?
 

What are the relations between dimensions and:
1. drain current,
2. transconductance,
3. current mirror ratio,
4. and finally how is the OTA transconductance defined?

When you finds the answers on this principle questions, think once again.
 

Drain current is proportional to W/L ratio
Transconductance is also proportional to W/L
Current mirror ratios are same
OTA transconductance is derivative of Io/derivative of vid
 

ICdesignerbeginner said:
Drain current is proportional to W/L ratio
Transconductance is also proportional to W/L
Current mirror ratios are same
OTA transconductance is derivative of Io/derivative of vid
Click to expand...

1. Correct
2. Correct
3. Wrong
4. Correct

Current mirror ratio is equal to ratio of W/L's of mirror mosfets. In this case the current mirror ratio is equal to (W/N×L)/(N×W/L)=1/N².
So, the OTA gm is N² times lower than gm of input transistor. The series (or stack) connection is an equivalent of length multiplication (as parallel connection is a W multiplication).
 

Current mirror ratios are same
Click to expand...

Surely this will help. [Source: Design of Analog CMOS Integrated Circuits, 2nd ed., B. Razavi, pp. 138]
mirrors.JPG
 

Thanks for your reply. I have tried to simulate the circuit figure is attached. I am operating these transistors in subthreshold region. The total current dividing in the parallel branches are 12nA but is the series transistor its 1.6nA. According to my understanding it should be 4nA similar to parallel transistor current (shown in figure attached). The series transistors are also having VDS<100mV for sub-threshold transistors to be in saturation. Only the top most series NMOS is in saturation lower two are in triode region (VDS<100mV). Can it be in triode? or in may also be in saturation.

seriesparallel.png
 

Dominik Przyborowski said:
12/9≈1.35 so, were is the issue? 1.6nA is a result of 10 times difference in V_DS.
Click to expand...

Thanks for your reply.

"1.6nA is the result of 10 times difference in V_DS". This point is confusing. I cant understand this point?

Should all the series transistors be in saturation? because my top most stacked transistor in series is in saturation remaining two lower series transistors are in triode?
 

Should all the series transistors be in saturation?
Click to expand...

No. What you have works properly. The three series transistors work as a composite device. You can verify this by analyzing this problem.
composite device.JPG
 

Thanks for your reply. I got your point but still the issue is the mode of operation of stacked transistors. I am operating all transistors in sub threshold region. Should all transistors be in subthreshold saturation? Because my top most stacked transistor is in saturation (vds>100mV) and remaining two lower transistors are in triode (vds<100mV).
 

The same principle applies to transistors in subthreshold operation. Imagine if all of them are in saturation (Vds>100mV), that would be like two current sources in series (Yikes!).
 

rmanalo said:
The same principle applies to transistors in subthreshold operation. Imagine if all of them are in saturation (Vds>100mV), that would be like two current sources in series (Yikes!).
Click to expand...

It means the top stacked transistors in series in saturation and the other two below transistors vds<100mV is ok. I dont have to make the lower two transistors to operate in saturation.

It means the simulation I have attached previously is OK.
 

rmanalo said:
No. What you have works properly. The three series transistors work as a composite device. You can verify this by analyzing this problem.
View attachment 148497
Click to expand...

How can this transistor be viewed as a single transistor? I have searched different articles showing that the VDS drop across these transistors are equal to a single voltage drop as shown in figure. Can you please help me in understanding this composite transistor? Is it due to the lower transistors operating in triode?
 

Draw a transistor layout which width is W, and length is 2L on paper. Now draw next to it 2 transistors with W width and L length, and connect them as the picture above. Try to merge the common source and drain terminals for smaller area. After all compare the left and right drawings, it should explain why they are the same.
 

What do you mean under "single transistor with respect to voltage drop"? I went through the attached link, but I have no idea what is this "self cascode". On the figure it is not a cascode. A cascode gate is connected to an AC ground, to get common-gate amplifier. If the gate of the top device is connected to the same AC signal it is not a cascode, just one transistor created from 2 transistors. That is all. Similarly if you connect paralel 2 transistors that is not a "self-enhancer", just 1 transistor from 2 transistors. Which you can also see on its layout.
 

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