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PCIE: split and merge AXI4 Stream based on physical function
Hi,
I would like to split and merge AXI4 Stream CQ, CC, RC, RQ of PCIE Gen3 shown below based on Physical function 0(PF0) and physical function 1(PF1) enabled during PCIE generation.
.s_axis_rq_tdata(s_axis_rq_tdata), // input wire [255 : 0] s_axis_rq_tdata
.s_axis_rq_tkeep(s_axis_rq_tkeep), // input wire [7 : 0] s_axis_rq_tkeep
.s_axis_rq_tlast(s_axis_rq_tlast), // input wire s_axis_rq_tlast
.s_axis_rq_tready(s_axis_rq_tready), // output wire [3 : 0] s_axis_rq_tready
.s_axis_rq_tuser(s_axis_rq_tuser), // input wire [59 : 0] s_axis_rq_tuser
.s_axis_rq_tvalid(s_axis_rq_tvalid), // input wire s_axis_rq_tvalid
.m_axis_rc_tdata(m_axis_rc_tdata), // output wire [255 : 0] m_axis_rc_tdata
.m_axis_rc_tkeep(m_axis_rc_tkeep), // output wire [7 : 0] m_axis_rc_tkeep
.m_axis_rc_tlast(m_axis_rc_tlast), // output wire m_axis_rc_tlast
.m_axis_rc_tready(m_axis_rc_tready), // input wire m_axis_rc_tready
.m_axis_rc_tuser(m_axis_rc_tuser), // output wire [74 : 0] m_axis_rc_tuser
.m_axis_rc_tvalid(m_axis_rc_tvalid), // output wire m_axis_rc_tvalid
.m_axis_cq_tdata(m_axis_cq_tdata), // output wire [255 : 0] m_axis_cq_tdata
.m_axis_cq_tkeep(m_axis_cq_tkeep), // output wire [7 : 0] m_axis_cq_tkeep
.m_axis_cq_tlast(m_axis_cq_tlast), // output wire m_axis_cq_tlast
.m_axis_cq_tready(m_axis_cq_tready), // input wire m_axis_cq_tready
.m_axis_cq_tuser(m_axis_cq_tuser), // output wire [84 : 0] m_axis_cq_tuser
.m_axis_cq_tvalid(m_axis_cq_tvalid), // output wire m_axis_cq_tvalid
.s_axis_cc_tdata(s_axis_cc_tdata), // input wire [255 : 0] s_axis_cc_tdata
.s_axis_cc_tkeep(s_axis_cc_tkeep), // input wire [7 : 0] s_axis_cc_tkeep
.s_axis_cc_tlast(s_axis_cc_tlast), // input wire s_axis_cc_tlast
.s_axis_cc_tready(s_axis_cc_tready), // output wire [3 : 0] s_axis_cc_tready
.s_axis_cc_tuser(s_axis_cc_tuser), // input wire [32 : 0] s_axis_cc_tuser
.s_axis_cc_tvalid(s_axis_cc_tvalid), // input wire s_axis_cc_tvalid
Is there any way to do this?
I am using Virtex ultrascale and first need to verify it in vivado 2018.1 simulator.
Hi,
I would like to split and merge AXI4 Stream CQ, CC, RC, RQ of PCIE Gen3 shown below based on Physical function 0(PF0) and physical function 1(PF1) enabled during PCIE generation.
.s_axis_rq_tdata(s_axis_rq_tdata), // input wire [255 : 0] s_axis_rq_tdata
.s_axis_rq_tkeep(s_axis_rq_tkeep), // input wire [7 : 0] s_axis_rq_tkeep
.s_axis_rq_tlast(s_axis_rq_tlast), // input wire s_axis_rq_tlast
.s_axis_rq_tready(s_axis_rq_tready), // output wire [3 : 0] s_axis_rq_tready
.s_axis_rq_tuser(s_axis_rq_tuser), // input wire [59 : 0] s_axis_rq_tuser
.s_axis_rq_tvalid(s_axis_rq_tvalid), // input wire s_axis_rq_tvalid
.m_axis_rc_tdata(m_axis_rc_tdata), // output wire [255 : 0] m_axis_rc_tdata
.m_axis_rc_tkeep(m_axis_rc_tkeep), // output wire [7 : 0] m_axis_rc_tkeep
.m_axis_rc_tlast(m_axis_rc_tlast), // output wire m_axis_rc_tlast
.m_axis_rc_tready(m_axis_rc_tready), // input wire m_axis_rc_tready
.m_axis_rc_tuser(m_axis_rc_tuser), // output wire [74 : 0] m_axis_rc_tuser
.m_axis_rc_tvalid(m_axis_rc_tvalid), // output wire m_axis_rc_tvalid
.m_axis_cq_tdata(m_axis_cq_tdata), // output wire [255 : 0] m_axis_cq_tdata
.m_axis_cq_tkeep(m_axis_cq_tkeep), // output wire [7 : 0] m_axis_cq_tkeep
.m_axis_cq_tlast(m_axis_cq_tlast), // output wire m_axis_cq_tlast
.m_axis_cq_tready(m_axis_cq_tready), // input wire m_axis_cq_tready
.m_axis_cq_tuser(m_axis_cq_tuser), // output wire [84 : 0] m_axis_cq_tuser
.m_axis_cq_tvalid(m_axis_cq_tvalid), // output wire m_axis_cq_tvalid
.s_axis_cc_tdata(s_axis_cc_tdata), // input wire [255 : 0] s_axis_cc_tdata
.s_axis_cc_tkeep(s_axis_cc_tkeep), // input wire [7 : 0] s_axis_cc_tkeep
.s_axis_cc_tlast(s_axis_cc_tlast), // input wire s_axis_cc_tlast
.s_axis_cc_tready(s_axis_cc_tready), // output wire [3 : 0] s_axis_cc_tready
.s_axis_cc_tuser(s_axis_cc_tuser), // input wire [32 : 0] s_axis_cc_tuser
.s_axis_cc_tvalid(s_axis_cc_tvalid), // input wire s_axis_cc_tvalid
Is there any way to do this?
I am using Virtex ultrascale and first need to verify it in vivado 2018.1 simulator.