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Post layout Simulation without Physical verification

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Mahmoud_Dagher

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I have my Digital Implementation from SoC Encounter with zero Geometry and Connectivity violations.
Is it possible to do the post layout Simulation without Physical verification on Calibre for example (without clean DRC,..) ?
 

You can simulate any layout that passes extraction. The issue is that extraction and LVS are tightly coupled together...
 

You can simulate any layout that passes extraction. The issue is that extraction and LVS are tightly coupled together...

Okay Thank you, when I run LVS I get an Error: Supply error detected. ABORT ON SUPPLY ERROR is specified - aborting. *** Calibre finished with Exit Code: 4 ***

What's the problem?
 

Probably missing properly defined globals for gnd/vdd
 

If the connectivity is not proper (possible supply short) then
there might be no value, but some cost, to running the sim
and making sense of "garbage input".

Tie your sneakers before you try to run.

You might try to find where that "abort on supply error is
specified", allowing it to run might lead you to using the
shorts tool or eyeballing the extracted view. But it seems
odd that a net short would not have shown up in the
extract phase (did you look?).
 

I have my Digital Implementation from SoC Encounter with zero Geometry and Connectivity violations.
Is it possible to do the post layout Simulation without Physical verification on Calibre for example (without clean DRC,..) ?

Technically, this is doable - doing layout only extraction (without cross-referencing to schematic), and running post-layout simulation (or some other simulations / analysis) on non-LVS-clean designs.

This is very useful for parasitics estimation at early design stages, when you do not have a complete design yet - but have much more freedom in optimizing interconnects.

But - you should be aware of the consequences, and the risks, i.e. you should know what you are doing.

While this is doable technically, logistically and politically this (non-LVS-clean) flow is often discouraged or even prohibited by CAD groups or EDA vendors, probably to minimize the risk of errors and responsibility.
 

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