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    Gating Signals for BSNPC inverter

    Hello,

    I am a newbie in PSpice and I want to know from you professionals that, is it possible to implement the signals given in the below figure?

    Click image for larger version. 

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    Kindly guide me. Any comment will be highly appreciated.

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    Re: Gating Signals for BSNPC inverter

    It's not difficult to find a pulse generator circuit which produces both waveforms (since one is an inverse of the other). For instance, the kind where one transistor turns on while the other transistor shuts off. Or a logic gate goes high while the other logic gate goes low.

    To create the final output state, you need to install some components in a strategic manner so as to interfere with oscillations more and more until they halt.



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    Re: Gating Signals for BSNPC inverter

    First of all, thank you for taking the taking the time to reply.
    Secondly, yes they are inverses of each other but not quite exactly the case because if you notice, the off-time of the first signal is more than the on-time of the second signal (that is after T/2).



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    Re: Gating Signals for BSNPC inverter

    There is a point where both signals are low. It's not obvious how to achieve this.

    To make one of them go high after a while, it is possible to create a delay by arranging a resistor-and-capacitor (sometimes adding a diode). There are multitude arrangements for such DRC networks. You can extend a pulse after the incoming pulse changes state, or you can create a ramping voltage upward or downward, etc.

    I'm pretty certain the exercise is intended to use the least number of components, and the most basic components. Of course the simple solution is to take a counter IC and make a 'count to 2 and hold', or 'count to 3 and hold'.



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    Re: Gating Signals for BSNPC inverter

    Hi,

    a picture with just some lines on it, no scales, no specifications....
    How can we know what is important and what is not important?

    Voltage levels, timings, rise time, fall time, delays....

    Klaus
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    Re: Gating Signals for BSNPC inverter

    Can you recommend any counter ICs in PSpice ?
    @KlausST yes, you are absolutely correct but to be honest there isn't anything mentioned like that at all in the research paper that we are trying to study and are trying to obtain the similar results as that of the paper.
    Here is the complete schematic and the circuit that we are implementing.
    Click image for larger version. 

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    Right now, I have generated the gating signals using the STIM-DIGI-CLOCK and have implemented the provided circuit on PSpice. Attached is the output of the PSpice program.
    Click image for larger version. 

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    I have tinkered with the caps, inductors and resistors but could not obtain a proper output signal.



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    Re: Gating Signals for BSNPC inverter

    Instead of doing this with an analog approach, you could consider having a look on digital synchronous designs; the circuit you want could me accomplished with a state machine (counter) made with FF's having 2 outputs S1 and S2 and perhaps a total of 11 states to be computed (5½ for each frame), and then returning to IDLE state after all. Perhaps unnecessary to say that clock rate should be twice (or quadruple) of the one shown at initial picture.
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    Re: Gating Signals for BSNPC inverter

    The circuit of the BSNPC inverter along with the gate drives is:
    Click image for larger version. 

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    and its corresponding output:
    Click image for larger version. 

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    I cant seem to be getting the negative half pulses of the modified sine wave.
    Also I want to ask, would it matter if the bidirectional switch is designed by using P-channel MOSFETs and the half bridge MOSFETs as N-channel (as opposed in the original figure given in previous post) ?
    Any comments will be much appreciated.



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    Re: Gating Signals for BSNPC inverter

    C2 is positioned between two ground icons (0V). Therefore it never charges.

    It looks as though this circuit is a push-pull which steps down 240 VDC to low VAC. THere is slow switching action combined with fast switching action. To test this concept it is best to start with simple artificial switches (rather than jump immediately to entire mosfet switching). Create clocks to drive it.

    This will allow you to make sure that component values result in your planned performance.

    Later you can add the mosfets. You need to experiment to find out where a P or N device works best, and how to provide correct biasing and a correct current return path, and how to handle inductive kick, how to handle power factor error, etc.



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    Re: Gating Signals for BSNPC inverter

    Thank you for the reply.
    Yes you are right but apparently if I do not apply the bottom ground of the C2 cap then this is the output:
    Click image for larger version. 

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    I had to attach this ground in order to get some viable output.

    Moreover, this circuit is not supposed to give to low VAC but apparently it does (which is of-course as you have mentioned earlier).
    Can you please explain what you mean by what is meant by "THere is slow switching action combined with fast switching action." ?



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    Re: Gating Signals for BSNPC inverter

    Three of the four power MOSFETs in your inverter need to be driven by isolated gate drivers because the gate voltage (+/- 20V maximum rating) has to be applied between gate and source of each transistor. Implementing the non-isolated post #8 circuit with real MOSFETs will end up in a nice cloud of smoke.

    Do I understand right that your question focusses on the gate driver and power circuit and implementing the control waveform as digital stimulation pattern is appropriate for the time being? The possible next abstraction level is using controlled voltage sources (E device) to generate the isolated gate voltage. Or do you want to implement real gate drivers with isolated supply voltage in Pspice?



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    Re: Gating Signals for BSNPC inverter

    The figure below depicts the basic concept (as far as the hardware is concerned):
    Click image for larger version. 

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    Does that "Isolate" the gate drives? Please do correct me if I am wrong.

    The goal is to design an inverter and obtain a "Modified Sine Wave" as given in post #6.
    I used different laptops to power the arduinos because I was told that it helps provide the isolation.



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    Re: Gating Signals for BSNPC inverter

    All four gate drivers are supplied by one power supply, so they surely don't provide isolated gate drive. I neither get the idea behind using multiple Arduinos. How should they generate synchronized waveforms? You need some kind of digital isolators, e.g. high speed opto couplers.



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    Re: Gating Signals for BSNPC inverter

    Electrically your scheme is starting to look correct as far as galvanic isolation. However it still exposes your expensive control devices to high voltage. It will be safer for your laptop computers if they get power from batteries.

    There is a chance that mains AC has an unseen path between your laptop power adapters, to your 120 VDC bipolar supply. THen your entire project completes the current path, possibly destroying every component, Arduino, and laptop. It's just a possibility since we don't know what safeguards are in place. However there's a real opportunity for disaster.



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    Re: Gating Signals for BSNPC inverter

    Quote Originally Posted by HiQureshi View Post
    modified sine wave.

    Also I want to ask, would it matter if the bidirectional switch is designed by using P-channel MOSFETs and the half bridge MOSFETs as N-channel (as opposed in the original figure given in previous post) ?
    This simulation creates a normal modified sinewave. It started with the section of your schematic (post #8) that does the conversion work, that is, the upper half.

    The P device is nearest the positive power supply. It turns on fully because it is driven by an N-device. It shuts off fully due to a pullup resistor to supply+.

    The flip-flop and logic gates convert a single incoming clock signal into two correct bias drivers for the push-pull half-bridge.

    My schematic does not address all concepts of your project, since you're trying to obtain more complicated driving waveforms. Can you confirm your goal is a normal modified sinewave? Our intention is to guide people's projects and not to hand them a solution.

    Also notice my simulation has low supply voltage. It is wise to start with low voltage rather than jump immediately to full house voltage.



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    Re: Gating Signals for BSNPC inverter

    Quote Originally Posted by FvM View Post
    All four gate drivers are supplied by one power supply, so they surely don't provide isolated gate drive. I neither get the idea behind using multiple Arduinos. How should they generate synchronized waveforms? You need some kind of digital isolators, e.g. high speed opto couplers.
    So I have to use three opto-couplers with the gate drivers having the same power source and I should use a single arduino for the waveform synchronization, would that solve the isolation problem?

    Quote Originally Posted by BradtheRad View Post
    The P device is nearest the positive power supply. It turns on fully because it is driven by an N-device. It shuts off fully due to a pullup resistor to supply+.

    The flip-flop and logic gates convert a single incoming clock signal into two correct bias drivers for the push-pull half-bridge.

    Also notice my simulation has low supply voltage. It is wise to start with low voltage rather than jump immediately to full house voltage.
    Are you talking about the schematic in post#8 (maybe partially), it would be helpful if you could provide your schematic that you are talking about?

    I tried different combinations of P and N-channel MOSFETs in the inverter circuit:
    Click image for larger version. 

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    The output:
    Click image for larger version. 

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    There is a DC Offset and the negative pulses are lesser in magnitude but nonetheless, I tried to add a CAP in series with the resistor at the output and this is the result:
    Click image for larger version. 

Name:	r.PNG 
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ID:	148859



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    Re: Gating Signals for BSNPC inverter

    Quote Originally Posted by BradtheRad View Post
    Can you confirm your goal is a normal modified sinewave?
    Yes apparently that is the goal for now.



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    Re: Gating Signals for BSNPC inverter

    Quote Originally Posted by BradtheRad View Post
    This simulation creates a normal modified sinewave. It started with the section of your schematic (post #8) that does the conversion work, that is, the upper half.

    The P device is nearest the positive power supply. It turns on fully because it is driven by an N-device. It shuts off fully due to a pullup resistor to supply+.

    The flip-flop and logic gates convert a single incoming clock signal into two correct bias drivers for the push-pull half-bridge.

    My schematic does not address all concepts of your project, since you're trying to obtain more complicated driving waveforms. Can you confirm your goal is a normal modified sinewave? Our intention is to guide people's projects and not to hand them a solution.

    Also notice my simulation has low supply voltage. It is wise to start with low voltage rather than jump immediately to full house voltage.
    Sorry, here's my image.

    Click image for larger version. 

Name:	D flip flop NOR gates drive NPN NPN-PNP mosfets push-pull modif sine 40VDC supply.png 
Views:	15 
Size:	25.0 KB 
ID:	148870



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    Re: Gating Signals for BSNPC inverter

    I tried to simulate your circuit on PSpice, please see your model:
    Click image for larger version. 

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    and the output of the simulation:
    Click image for larger version. 

Name:	ur.PNG 
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ID:	148885

    I also tried using MOSFETs to do the job but the result was not plausible. I also tried to accomplish the same task with JFETs and "somewhat" got "some" result.
    I am not sure what mistake I made. Please suggest a fix.



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    Re: Gating Signals for BSNPC inverter

    The idea behind the three level inverter is to have capacitors with sufficient capacitance that keep the voltage almost constant during the cycle. But your capacitors are small and you are driving the circuit much too slow.



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