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lw, sw in a processor

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stanford

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For pipelined architecture, which has fetch, decode, execute, mem (access mem), wr regs (write regs), that takes 1 clock cycles each. I'm confused about mem and wr regs.

1. if we have lw or sw, they get executed in the 'mem' phase. If it's a cache hit, it takes 1 clock cycle, and if its a cache miss, it can take a long time and stall. Is this correct?

2. for wr regs, do we write to registers that are separate from the cache? and this always takes 1 clock cycle?
 

1. yes - although stores don't necessarily need to stall in a non-trivial cache
2. yes
 

1. yes - although stores don't necessarily need to stall in a non-trivial cache
2. yes

So why do we need store load queue if we are going to cache? Is store load queue only used for when there is cache miss?
 

1. Most of the modern microprocessors are not as simple as 5 stage pipelines. In practice most companies design Out-of-order processors where you fetch in order, execute out of order and commit in order. Regardless, cache miss will take more clock cycle as cache block should be brought from lower level caches. However, we generally use non blocking caches which means that processor can continue with more cache requests. However, coherency and hazard resolutions have highest priority. We do have load store buffers to resolve hazards like RAW, WAW and WAR in OOO processors. Assume that there is a store instruction in lw-sw buffer whose address is still not computed. A load instruction (instruction after store) cannot read from cache until we know address of store instruction. This is to avoid RAW dependency. For 5 stage pipeline, there are only RAW hazards and you can have hazard detection units to stall or forwarding units to forward the data.

2. For you Wr reg question, we do have register files where you can write. These are separate from caches.

Let me know if you need more details.

Thanks,
Abhishek
 

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