stanford
Full Member level 2
For pipelined architecture, which has fetch, decode, execute, mem (access mem), wr regs (write regs), that takes 1 clock cycles each. I'm confused about mem and wr regs.
1. if we have lw or sw, they get executed in the 'mem' phase. If it's a cache hit, it takes 1 clock cycle, and if its a cache miss, it can take a long time and stall. Is this correct?
2. for wr regs, do we write to registers that are separate from the cache? and this always takes 1 clock cycle?
1. if we have lw or sw, they get executed in the 'mem' phase. If it's a cache hit, it takes 1 clock cycle, and if its a cache miss, it can take a long time and stall. Is this correct?
2. for wr regs, do we write to registers that are separate from the cache? and this always takes 1 clock cycle?