Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

FPGA build with makefiles. The exported variable problem

Status
Not open for further replies.

wtr

Full Member level 5
Joined
May 1, 2014
Messages
299
Helped
29
Reputation
58
Reaction score
25
Trophy points
1,308
Activity points
4,108
Hello all,

I am aware that makefiles commands run in separate shells. However is it possible to get an exported variables into my next make target?

Code:
#Makefile
#somefile.mk will set $LOG_DIR & $SCRIPT_DIR
include somefile.mk

test:  
   export LOG_DIR=$(LOG_DIR); \
   .  $(SCRIPT_DIR)/set_env_var.sh

test2: test
   export LOG_DIR=$(LOG_DIR); \
   . $(SCRIPT_DIR)/write_variables.sh
Where set_env_var.sh does
Code:
XXXXXVARIABLE=somevalue            
export XXXXXVARIABLE               
set > $LOG_DIR/variables_out1.log
Where write_variables.sh does
Code:
YYYYYYVARIABLE=somevalue
export YYYYYYVARIABLE
set > $LOG_DIR/variables_out2.log

Basically want I'm trying to do is populate the current shell with a set of environment variables, that waterfall from one make target to the next. Such that variables_out2.log has YYYYYYVARIABLE AND XXXXXVARIABLE

Eventually the finally call will be a tcl script which will utilise the ::env(WHATEVER_VARIABLE) for the build of the FPGA.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top