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  1. #1
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    "np" layer and "pp" layer in CMOS circuit

    Hi Everyone
    I am laying-out a clocked circuit with TSMC 65 nm PDK. I noticed there are np layer (n+ S/D iron implantation) and pp layer(p+ ion implantation ). And I have heard that for the layout of a series connected inverters, for example, it's better to layout all the PMOS in a big nwell by connecting all the small nwells together.

    My question is as follow:
    1. Should I try to make a big np/pp drawing to connect all the np/pp from each small inverters together?

    2. The nmos is layout in the np layer but its body contact is layout in pp drawing. Same for pmos, which is layout in pp drawing but the body contact is in np drawing. (because it is a contact used to bias a P-type substrate(Psub) )
    Is there any pros or cons if the np drawing of a nmos (source/drain ion implantation) is connect to the np drawing of the pmos's bulk connect?

    Thanks
    Allen

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  2. #2
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    Re: "np" layer and "pp" layer in CMOS circuit

    1) No, use metal. You can end up with significant unmodeled
    series resistance.

    2) You would have to have an "active area" path from nmos.np
    to pmos.np and this will surely violate the rules about active
    spacing from, or nesting within, Nwell. Active doesn't get to
    cross NWell.



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  3. #3
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    Re: "np" layer and "pp" layer in CMOS circuit

    Hi dick_freebird
    Thanks for the reply,
    1) What about nwell? Should I connect them together since your argument of "significant unmodeled series resistance" may happen here as well?
    2) I am a bit confused about your point. Please look at the picture

    Click image for larger version. 

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    The thin white squares are np for nmos S/D and np for pmos nwell contact. The red square marked as "np to connect" is my option to connect 2 np area together. There is no active area path and the DRC/ERC all passed.

    Can you please elaberate your point further?

    Thanks
    Allen



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    Re: "np" layer and "pp" layer in CMOS circuit

    All of your logic gates will share one big nwell. You won't need a nwell/sub tie for every gate. The layout design rules should specify the max distance between ties. You may add them as you have them now or put them under the power buses. Do you have a standard cell library with a DFF that you can use as an example?

    Not sure why you want to connect the NP layers as you have drawn. As long as they meet the spacing requirement you are good to go.



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    Re: "np" layer and "pp" layer in CMOS circuit

    Thanks for your reply!
    “Not sure why you want to connect the NP layers as you have drawn.”
    The truth is I don't want to. It's some DRC rules that make that connection necessary unless I change some layout. I just wonder if I connect it like that, are there any pros or cons associated with it?

    Thanks a lot



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