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11th July 2018, 19:58 #1
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latency of the dsync output
Do we expect output of dsync to get the stable input after 2 or 3 destination clks? Are there any other practical cases we should consider?

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11th July 2018, 22:21 #2
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Re: latency of the dsync output
No idea what you are talking about... context?
Really, I am not Sam.

11th July 2018, 22:31 #3
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12th July 2018, 08:16 #4
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Re: latency of the dsync output
We don't know what is "dsync"!
Please frame your question properly with a proper background explanation or reference (if needed).FPGA enthusiast!

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12th July 2018, 08:35 #5
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12th July 2018, 15:57 #6
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12th July 2018, 18:07 #7
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12th July 2018, 22:22 #8
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Re: latency of the dsync output
Why don't you sketch a timing diagram?

12th July 2018, 22:49 #9
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17th July 2018, 19:30 #10
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Re: latency of the dsync output
For a double sync you should ideally see the output after 2 destination clocks. However, when you move from one clock domain to other, synchornizers make sure that probability of metastability will be reduced to almost 0, but they do not guarantee that data will be sampled in 2 clock cycles. Data may take more time than that.
Thanks,
Abhishek
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