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latency of the dsync output

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stanford

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Do we expect output of dsync to get the stable input after 2 or 3 destination clks? Are there any other practical cases we should consider?
 

No idea what you are talking about... context?
 

No idea what you are talking about... context?

After you see a change on d input of dsync, how many destination clk cycles does it take to see a change on the output?
 

We don't know what is "dsync"!
Please frame your question properly with a proper background explanation or reference (if needed).
 

We don't know what is "dsync"!
Please frame your question properly with a proper background explanation or reference (if needed).

back to back flops (synchronizer) on clk1 with async input at d pin. When async input changes, you may see output change after 2-3 clks. Is this correct?
 

back to back flops (synchronizer) on clk1 with async input at d pin. When async input changes, you may see output change after 2-3 clks. Is this correct?

Who knows. Check the documentation of the library. A synchronizer can have any number of stages...
 

Why don't you sketch a timing diagram?


async input
_________|----------------------------------------

clk
_________|------|____|------|____|------|____|

case 1
______________________|----------------------

case 2
________________________________|-------
 

For a double sync you should ideally see the output after 2 destination clocks. However, when you move from one clock domain to other, synchornizers make sure that probability of metastability will be reduced to almost 0, but they do not guarantee that data will be sampled in 2 clock cycles. Data may take more time than that.

Thanks,
Abhishek
 

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