Pravesh_Rathee
Newbie level 5
Hii,
i am making module that compares two numbers using inbuilt operator of verilog. I am making the module synchronous with clock. The design is quite simple.After writing code the code and synthesising it which I have attached below I am obtaining the output at 9th clock cycle. I am expecting my output to be at next clock cycle . In behavioral simulation , I my getting expected output but after doing synthesis,results are totally changed(obtained output at 9th clock cycle). Also,from testbench if you give inputs for testing at every rising edge then in Post synthesis simulation, it shows output for only last inputted values.
Kindly will anyone explain why is it happening so.
RTL Code :
RTL Testbench:
i am making module that compares two numbers using inbuilt operator of verilog. I am making the module synchronous with clock. The design is quite simple.After writing code the code and synthesising it which I have attached below I am obtaining the output at 9th clock cycle. I am expecting my output to be at next clock cycle . In behavioral simulation , I my getting expected output but after doing synthesis,results are totally changed(obtained output at 9th clock cycle). Also,from testbench if you give inputs for testing at every rising edge then in Post synthesis simulation, it shows output for only last inputted values.
Kindly will anyone explain why is it happening so.
RTL Code :
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module comp (clk,a,b,out); input clk; input[15:0] a,b; output reg [15:0] out; always @(posedge clk ) begin if(a>b) out<=a; else out<=b; end endmodule
RTL Testbench:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module testbench( ); reg clk; reg [15:0] a,b ; wire [15:0] out; comp #(16,6) PUT (clk,a,b,out); initial begin clk=1; #10 a=16'd4144; b=16'd234; #10 a=16'd144; b=16'd134; end always #5 clk=~clk; endmodule