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Comparing two numbers

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Pravesh_Rathee

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Hii,
i am making module that compares two numbers using inbuilt operator of verilog. I am making the module synchronous with clock. The design is quite simple.After writing code the code and synthesising it which I have attached below I am obtaining the output at 9th clock cycle. I am expecting my output to be at next clock cycle . In behavioral simulation , I my getting expected output but after doing synthesis,results are totally changed(obtained output at 9th clock cycle). Also,from testbench if you give inputs for testing at every rising edge then in Post synthesis simulation, it shows output for only last inputted values.
Kindly will anyone explain why is it happening so.


RTL Code :

Code Verilog - [expand]
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module comp (clk,a,b,out);
input clk;
input[15:0] a,b;
output reg [15:0] out;
 
always @(posedge clk )
begin
if(a>b)
out<=a;
else 
out<=b;
 
end
endmodule


RTL Testbench:


Code Verilog - [expand]
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module testbench( );
reg clk;
reg [15:0] a,b ; 
wire [15:0] out;
 
comp  #(16,6) PUT (clk,a,b,out);
 
initial
begin
 
clk=1;
#10
 
a=16'd4144;
b=16'd234;
#10
a=16'd144;
b=16'd134;
 
end
always 
#5 clk=~clk;
 
endmodule
 

The code you posted for the module has no parameters, the testbench instance has.
 

stanford said:
How does this change the behavior of the code?
Click to expand...

It means the OP is simulating something different than what he posted. God only knows what. The posted coded is trivial, there is no reason for any different result to appear after the 9th cycle or Nth cycle for that matter.
 

hi,

. In behavioral simulation , I my getting expected output
Click to expand...
with the above code how you are getting results at 10th clock cycle ?
you are expecting output at 10th clock cycle right ? (in simulation)
are you missing some delay in testbench?

thanks and regards
 

In behavioral simulation, I am getting result at next clock cycle.But after synthesis results get change, I see my output at 9th clock cycle.In Behavioral simulation , i get the output at next clock cycle.I want both the results to be same.
I suggest you to simulate the code and see yourself the results in both behavioral and post synthesis.
 

hi,
I am obtaining the output at 9th clock cycle. I am expecting my output to be at next clock cycle .
Click to expand...
:smile: :confusion.

so
Also,from testbench if you give inputs for testing at every rising edge then in Post synthesis simulation, it shows output for only last inputted values.
Click to expand...
in post simulation give enough delay . you had only given 1 clockcycle delay.
initial
begin

clk=1;
a=0;
b=0;
#100

a=16'd4144;
b=16'd234;
Click to expand...
make it to 100 or above 100 and check your results again. I think you will be able to see all your outputs.


thanks and regards
 

Pravesh_Rathee said:
In behavioral simulation, I am getting result at next clock cycle.But after synthesis results get change, I see my output at 9th clock cycle.In Behavioral simulation , i get the output at next clock cycle.I want both the results to be same.
I suggest you to simulate the code and see yourself the results in both behavioral and post synthesis.
Click to expand...

That's just not possible. You are simulating it wrong.
 

thankyou..I am glad finally you reached at the result beacuse of which I started this thread. Now can you explain why i will have to give delay of 100 and above. Only if I give delay of 100 then I will see the correct outputs in post synthesis simulation. Why not less than 100 or any value below it or why not if I give input at just next clock cycle.
 

I request you to please simulate the code ,it just lies in the post and see yourself. I am simulating the code in vivado xilinx simply . Simply saying you are simulating it wrong , doesn't make any sense . I think "dipin" has reached the point what I am asking.
 

Pravesh_Rathee said:
I request you to please simulate the code ,it just lies in the post and see yourself. I am simulating the code in vivado xilinx simply . Simply saying you are simulating it wrong , doesn't make any sense . I think "dipin" has reached the point what I am asking.
Click to expand...

I refuse to do your homework. I will, however, repeat myself: the behavior you are reporting here is not possible for this circuit. Its operation does not change after 9 cycles. You are doing something wrong elsewhere. Go debug your simulation.
 

Adding delay into the testbench as dpin is suggesting isn't going to do anything useful especially if the netlist simulation is done using unit delays and not a full timing SDF simulation. Even then adding 100 isn't reasonable as the clock toggles at 5.

I suppose this could be a timing simulation with an SDF and the simulation is being run at ps resolution so the clock is actually at 100GHz (given you have no timescale specified in either file). If that is the case it probably does take more than 100 ps of delay to even get the simulation to output data. Once again the problem isn't the comp.v code but is a lack of understanding on how to simulate a design and/or write a testbench.

Along the lines of not knowing how to write a testbench you assign your inputs at the rising clock edge, i.e. at #10 and #20. This is going to result in race condition with your clock and data in your simulation and will make your simulations look goofy. In this case the simulation probably has inputs being applied on the first clock edge and the output showing up on that same clock edge instead of on the next clock edge.
 

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