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Proteus testing port input signal and timer 0 as a counter all not working!

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eagle1109

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Hello,

I'm doing some tests in proteus, I did timer 0 as a timer with overflow test.

I know proteus isn't perfect and could have some faults.

I can take out the testboard and check the results in real, but I thought it would be much more simple to do them in software.

Two tests didn't work, I think I did all the proper SFRs configurations:
1. Testing port input signal on PORTA and produce an output on PORTD.
2. Configure timer 0 as a counter with a digital clock input on PORTA pin RA4.

Here's my code and circuit:

The code didn't show complete with code icon, so I include the code with PHP icon.


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/* Main.c file generated by New Project wizard
 *
 * Created:   Wed Jul 11 2018
 * Processor: PIC18F4550
 * Compiler:  MPLAB XC8
 */
 
#include <xc.h>
#define _XTAL_FREQ 4000000
unsigned char counter = 0;
void main(void)
 {
    ADCON0=0x00;
    ADCON1=0x00;
    CMCON=0x07;
    T0CON=0xA0;
    INTCON=0xE0;
    TRISD=0x00;
    TRISA=0x12;
    TRISB=0x0F;
   while (1)
   {
      if (PORTBbits.RB0=1)
      {
     PORTDbits.RD1=1;
     __delay_ms(10);
     PORTDbits.RD1=0;
      }
    
      if (T0CON&(1<<TMR0IF)==1)
      {
     T0CON&(1<<TMR0IF)==0;
     counter++;
     if (counter==10)
     {
        PORTDbits.RD0=1;
        __delay_ms(10);
        PORTDbits.RD0=0;
     }
      }
   }
 }



proteusCKT.png
 
Last edited by a moderator:

Where are the CONFIG bits set ?

You have to use LATxbits.LATxy for output ports and pins in PIC18F.

Have you disabled ADC module ?
 
There is a syntax error at the following expression, where you should use '==' instead of '='

Code:
if (PORTBbits.RB0=1)

- - - Updated - - -

BTW, I just removed the PHP formatting, 'C' syntax highlighter is the one suited.
 
Where are the CONFIG bits set ?
You have to use LATxbits.LATxy for output ports and pins in PIC18F.
Have you disabled ADC module ?
I think they are not necessary because the mcu is working without them. And I don't think that there are config bits for ADC module.

Here's an example config bits I just got from MPLAB x for the PIC18F4550:
Code:
// CONFIG1L
#pragma config PLLDIV = 1       // PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
#pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
#pragma config USBDIV = 1       // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)

// CONFIG1H
#pragma config FOSC = INTOSC_XT // Oscillator Selection bits (Internal oscillator, XT used by USB (INTXT))
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOR = OFF        // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
#pragma config BORV = 3         // Brown-out Reset Voltage bits (Minimum setting 2.05V)
#pragma config VREGEN = OFF     // USB Voltage Regulator Enable bit (USB voltage regulator disabled)

// CONFIG2H
#pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = ON      // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = ON      // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
#pragma config LPT1OSC = OFF    // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = OFF      // MCLR Pin Enable bit (RE3 input pin enabled; MCLR pin disabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
#pragma config ICPRT = OFF      // Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
#pragma config CP2 = OFF        // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
#pragma config CP3 = OFF        // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
#pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
#pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)

I pasted them in Proteus and it's the same.

Here're my SFR for the ADC and comparators configuration to turn them off.

Code:
ADCON0=0x00;CMCON=0x07;

OK, wait a minute!! I forgot to configure the bits of ADCON1 to 0x0f as in the datasheet.

Oh, lol ... it's a simple mistake sorry :thumbsup:

Now the digital input problem is solved now with the timer 0 clock input to work as a counter.


There is a syntax error at the following expression, where you should use '==' instead of '='

Code:
if (PORTBbits.RB0=1)

- - - Updated - - -

BTW, I just removed the PHP formatting, 'C' syntax highlighter is the one suited.

Yes, the CODE option didn't give me full range of text this afternoon, I think it's working now.

For the syntax error, I just applied the direct way of testing the same port as follows:
Code:
      if (PORTA==0x01)
      {
	 LATB=0x40;
	 __delay_ms(10);
	 LATB=0x00;
      }

It works OK.
 

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