Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Encrypt verilog with ablity to synthesize in cadence tool

Status
Not open for further replies.
S

smsskil

Newbie level 3
Joined
Jul 11, 2018
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
32
is it possible to encrypt verilog code but can be synthesized in cadence? I need to give my design to customer for his integrating. But I don't know how can i protect my file

Any help?
 

Yes - but basically you need to encrypt it once each for Cadence / Synopsys / Mentor. Search for 'pragma protect'
 

jbeniston said:
Yes - but basically you need to encrypt it once each for Cadence / Synopsys / Mentor. Search for 'pragma protect'
Click to expand...
Hi jbeniston,
I have searched pragma protect,noticing that there are many posts mention ncprotect.
But the question is,can ncprotect output file that can be synthesized? Or there are other software to do this...
 

smsskil said:
is it possible to encrypt verilog code but can be synthesized in cadence?
Click to expand...
Possible as far as you use Cadence Tools in all stage s of design.

To encrypt verilog, use "ncprotect" command.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top