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How to model a time dependent impulse current source in hspice

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k_jam2662

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I want to model an impulse current source in hspice so that the startup time is determined as follows:
If dt<0, current source will be on.
Where dt=th-tf,
th:is the time has been passed from beginning of the simulation ,
tf=1/v(3),
Where v(3) is voltage of the node named 3,
This if condition must be checked for every step time of the transient simulation.
Whenever this condition is met, th must be reset to zero.
Can this behavior be modeled in hspice?
How the hspice code can be written?
 

I have a circuit which includes two capacitors, current impulse source and a time dependent voltage source.
One of the capacitor is parallel to the current source,
The problem is how to design this current impulse source in hspice because the start time of the pulses are not fixed and predetermined values.
They are obtained in a iterative process as follows :
For each step of transient simulation in hspice, a new voltage of the capacitors are calculated, then a time called tf is calculated as tf =1/V(c1),Where v(c1)is voltage of the capacitor 1,
After that the difference between "tf "and the time has been passed from beginning of the transient simulation until now called "th" is calculated, if this difference is positive the above procedure is repeated. Else if it is negative, the start time of the current source set.
After that "th" resets to zero and the above procedure is repeated,
How can I implement this behavior in hspice? How the code must be written?
 

I don't know how l can save time between two consecutive impulses, this is the problem because this time must be saved in each step such as a counter, and also a comparison between th and tf must be done.
When the negative condition is met, the counter must reset to zero. And the before mentioned procedure is repeated until determining the start time for the next impulse.
The main problem is that I don't know how l can write the above mentioned else if condition in the hspice?
For counting the step times in transient simulation in hspice and saving this parameter (which is named "th")what can I do?
 

Where dt=th-tf,
th:is the time has been passed from beginning of the simulation ,
What do you want to describe as "th" ?

This if condition must be checked for every step time of the transient simulation.
What do you want to mean ?
Describe sentences correctly.

Whenever this condition is met,
th must be reset to zero.
This is contradictory.
Describe sentences correctly.

then a time called tf is calculated as tf =1/V(c1),
What do you want to mean ?
Describe sentences correctly.

After that the difference between "tf "and the time has been passed from beginning of the transient simulation
until now called "th" is calculated,
What do you want to mean ?
Describe sentences correctly.


I think a signal which you want to realize is no more than an event triggered pulse.

Again describe sentences correctly.

The main problem is that I don't know how l can write the above mentioned else if condition in the hspice?
No.
If so, describe it by other languages such as C#, C++, C, MATLAB, etc.

I think what you want to do is no more than very easy thing.

HSPICE has Verilog-A.
Use Verilog-A.

Again describe sentences correctly.
Again describe sentences correctly.
Again describe sentences correctly.
 
Last edited:

Assume we have a current source which includes several impulses, there is a time between every two consecutive impulses, this time is measured after ending past impulse and before starting the future impulse. This time must be saved and named as "th",,this time is determined by a counter and it's value increases in each step time of the transient simulation.
Hence, this time is not a given time.
in each step time, after calculating the new values of the voltage of the capacitors, an other time named "tf" is calculated. After that a condition is investigated, if this condition is not met, the counter is increased by one and new voltages are calculated again.
But if the condition is met, the counter resets to zero and the strat time of the impulse is found.
This procedure must be repeated to find the other start times while the simulation end time reaches.
*****************
I think a signal which you want to realize is no more than an event triggered pulse.

Yes,you are right. I need to model a time dependent current source which may have some impulses. The start times of these impulses are not known. The problem is to find these start times by an algorithm mentioned in the second post.
As you said, each impulse is exactly determined after an event happened.
******************

No.
If so, describe it by other languages such as C#, C++, C, MATLAB, etc.

I write this code in matlab and it works correctly, however I want to have a component or block in hspice which has a similar behavior.
The circuit model is my aim.
************
I think what you want to do is no more than very easy thing.
HSPICE has Verilog-A.
Use Verilog-A.

How can I insert a vrilog A code with in my hspice code?
Would you please give me an easy hspice netlist example which includes an else if condition?
 

Reread your sentences surely.
Do you think there is anyone who can understand meanings of your sentences ?

this time is measured after ending past impulse and before starting the future impulse.
How do you define ending and starting ?
Surely consider.

I write this code in matlab and it works correctly,
Show me MATLAB m-file.
I will translate it to Verilog-A.

Simulink and MATLAB are diifferent product.

I can also translate Simulink model to Verilog-A, if you truely understand Simulink correctly.

How can I insert a vrilog A code with in my hspice code?
".hdl" statement.

Would you please give me an easy hspice netlist example which includes an else if condition?
See HSPICE document.
**broken link removed**

Code:
// VerilogA for Test, Transponder_Signals, veriloga

`include "constants.vams"
`include "disciplines.vams"

`define		Nums_of_Plucking	8

module Transponder_Signals(induced_current_p, induced_current_n, fdevsw, lfmodin);
inout induced_current_p, induced_current_n;
output fdevsw, lfmodin;
electrical induced_current_p, induced_current_n;
voltage fdevsw, lfmodin;

parameter real fc=134.2k from (0:inf);
parameter real Ac=80u from (0:inf);
parameter real duration=150m from [0:inf);

parameter real logic_high_level=6.0 from (0:inf);

parameter real Tlow_for_fdevsw=118.8u;
parameter real Thigh_for_fdevsw=129.3u;
parameter real Tdelay_for_fdevsw=duration + 300u;
parameter real Trise_for_fdevsw=Tlow_for_fdevsw/1000;
parameter real Tfall_for_fdevsw=Tlow_for_fdevsw/1000;

parameter real fres_for_low=134.2k;
parameter real fres_for_high=125k;
parameter real Tdelay_for_low=0.0;
parameter real Tdelay_for_high=0.0;
parameter real Twidth_for_low=(1/fres_for_low)/4;
parameter real Twidth_for_high=(1/fres_for_high)/4;
parameter real Trise_for_low=Twidth_for_low/100;
parameter real Trise_for_high=Twidth_for_high/100;
parameter real Tfall_for_low=Twidth_for_low/100;
parameter real Tfall_for_high=Twidth_for_high/100;

parameter real period_of_plucking_for_low=Tlow_for_fdevsw/`Nums_of_Plucking from (0:inf);
parameter real period_of_plucking_for_high=Thigh_for_fdevsw/`Nums_of_Plucking from (0:inf);

real logic_low_level;
real vout_val_for_fdevsw;
real turn_off_for_high[1:`Nums_of_Plucking];
real turn_off_for_low[1:`Nums_of_Plucking];
real vout_val_for_high[1:`Nums_of_Plucking];
real vout_val_for_low[1:`Nums_of_Plucking];

real time1, time2, local_time;
genvar i;

voltage fdevsw_int, lfmodin_int;
real aho1, aho2;
integer iflag1, iflag2;
integer my_edge;

analog begin
   $bound_step((1/fc)/16.0);

   @(initial_step) begin
      my_edge = -1;
      iflag1 = 0;
      iflag2 = 0;
      time1 = -1G;
      time2 = -1G;
      logic_low_level = 0.0;
      vout_val_for_fdevsw = logic_low_level;
      for(i=1; i<=`Nums_of_Plucking; i=i+1) begin
         vout_val_for_high[i] = logic_low_level;
         turn_off_for_high[i] = -1M;
         vout_val_for_low[i] = logic_low_level;
         turn_off_for_low[i] = -1M;
      end
   end // initial_step

   if($abstime <= duration) begin
      I(induced_current_p, induced_current_n) <+ -Ac*sin(2*`M_PI*fc*$abstime);
   end
   else begin
      I(induced_current_p, induced_current_n) <+ 0.0;
   end

   @(timer(Tlow_for_fdevsw, Tlow_for_fdevsw+Thigh_for_fdevsw)) begin
      vout_val_for_fdevsw = logic_high_level;
   end 

   @(timer(Tlow_for_fdevsw+Thigh_for_fdevsw+Trise_for_fdevsw, Tlow_for_fdevsw+Thigh_for_fdevsw)) begin
      vout_val_for_fdevsw = logic_low_level;
   end 

   V(fdevsw) <+ transition(vout_val_for_fdevsw, Tdelay_for_fdevsw, Trise_for_fdevsw, Tfall_for_fdevsw);

   @(cross(V(fdevsw)-logic_high_level/2, +1)) time1 =  $abstime;
   @(cross(V(fdevsw)-logic_high_level/2, -1)) time2 =  $abstime;

   for(i=1; i<=`Nums_of_Plucking; i=i+1) begin
/*
      if($abstime < duration) begin
        vout_val_for_high[i] = logic_low_level;
        turn_off_for_high[i] = -1M;

        vout_val_for_low[i] = logic_low_level;
        turn_off_for_low[i] = -1M;
      end
      else begin
*/
        local_time = time1 + (i-1)*period_of_plucking_for_high;
        @(timer(local_time)) iflag1 = 1;
        @(cross(V(induced_current_p, induced_current_n), my_edge)) begin
          if(iflag1 == 1) begin
            vout_val_for_high[i] = logic_high_level;
            aho1 = $abstime;
            iflag1 = 0;
          end
        end
        turn_off_for_high[i] = aho1 + Twidth_for_high + Trise_for_high;
        @(timer(turn_off_for_high[i])) vout_val_for_high[i] = logic_low_level;

        local_time = time2 + (i-1)*period_of_plucking_for_low;
        @(timer(local_time)) iflag2 = 1;
        @(cross(V(induced_current_p, induced_current_n), my_edge)) begin
          if(iflag2 == 1) begin
            vout_val_for_low[i] = logic_high_level;
            aho2 = $abstime;
            iflag2 = 0;
          end
        end
        turn_off_for_low[i] = aho2 + Twidth_for_low + Trise_for_low;
        @(timer(turn_off_for_low[i])) vout_val_for_low[i] = logic_low_level;
      //end
      V(lfmodin) <+ transition(vout_val_for_high[i], Tdelay_for_high,
                               Trise_for_high, Tfall_for_high)
                  + transition(vout_val_for_low[i], Tdelay_for_low,
                               Trise_for_low, Tfall_for_low);
   end

end // analog begin

endmodule
 
Last edited:

Reread your sentences surely.
Do you think there is anyone who can understand meanings of your sentences ?
I apologize for any mistake in my sentences,
My mean is the time between the previous and the next impulse,

How do you define ending and starting ?
Surely consider.
Whole the procedure is done in a loop, and there is a counter for each current source.
I don't have any information about the starting time of each impulse and it must be found in a loop.
However we have ;
End time =start time +a constant

Show me MATLAB m-file.
I will translate it to Verilog-A.
Okay, I will send it, thanks for your kindly help.

Simulink and MATLAB are diifferent product.

I can also translate Simulink model to Verilog-A, if you truely understand Simulink correctly.

".hdl" statement.
Thanks.

See HSPICE document.
**broken link removed**
Thanks.

Code:
// VerilogA for Test, Transponder_Signals, veriloga[/QUOTE]
Thanks
 
Last edited by a moderator:

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