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In the paper, the author didn't mentioned about the sizing of the transistor. Instead, he gave the total width. So, how can I calculate the individual widths for nmos and pmos.
Please find the below attachments.
You would have to make some assumptions or find some
additional info such as the P:N width ratio (like, is min W
the thing, or is it equal drive strength, and indeed can any
valid generalization be made? Inverters are often designed
for equal drive, but the sense latch, maybe not? Could even
be a mixed bag (e.g. balanced inverter but all-minimum pass
gate, etc.).
There's also the problem of 4 circuits, 5 data list columns
and a fair bit of mismatch between names and acronyms
for some (not to mention the transistor count discrepancy
between what's shown and what's said).
On the other hand the width/N (~ W) looks fairly consistent
at about 2 - 2.5 and you might wonder just how close you
really need to be, to get "good enough".
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