stanford
Full Member level 2
Is below correct for initializing fifo and is this synthesizable?
Code:
logic [4:0] wptr;
logic [7:0] mem [15:0];
genvar i;
always_ff @(posedge wclk or negedge wrst)
if (!wrst)
for (i=0;i<16;i=i+1)
mem[i] <= '0;
else if (winc && !full)
mem[wptr[3:0]] <= wdata[7:0];