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test bench for an Adder

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B21hasni

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Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is 
port(
a : in std_logic_vector (15 downto 0);
b : in std_logic_vector (15 downto 0);
s : out std_logic_vector (15 downto 0);
cf : out std_logic;
ovf : out std_logic
);
end adder;

architecture adder of adder is
begin
process (a,b)
variable temp: std_logic_vector (16 downto 0);
begin 
temp := ('0'& a) + ('0'& b);
s<= temp(15 downto 0);
cf<= temp(16);
ovf<= temp(15) xor a(15) xor b(15) xor temp (16);
end process;
end adder;

How can Iwrite a test bench for the above design?
 

error while compiling test bench

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder_tb is
end adder_tb;
architecture adder_16b of adder_tb is
component adder
port(
a : in std_logic_vector (15 downto 0);
b : in std_logic_vector (15 downto 0);
s : out std_logic_vector (15 downto 0);
cf : out std_logic;
ovf : out std_logic
);
end component;
signal a : std_logic_vector (15 downto 0):= "0000000000000000";
signal b : std_logic_vector (15 downto 0):= "0000000000000000";
signal s : std_logic_vector (15 downto 0):= "0000000000000000";
signal cf : std_logic := '0';
signal ovf : std_logic := '0';
begin
UUT: adder port map (a=>a, b=>b, s=>s, cf=>cf, ovf=>ovf);
adder_pro:process
begin
a<="0000000000000000"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000001"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000010"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000011"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000100"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000101"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000110"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000111"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001000"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001001"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001010"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001011"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001100"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001101"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001110"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001111"; b<="0000000000000000"; wait for 10ns;
wait;
end process;
end;

When I compiled the above test bench I got this error

Error (10533): VHDL Wait Statement error at adder_tb.vhd(25): Wait Statement must contain condition clause with UNTIL keyword
 
Last edited by a moderator:

There are many examples on the internet for writing testbenches.
You need to write code that generates data for the inputs at the very least. A self checking testbench would also somehow generate the expected data and compare it to the output from the design.

an example of basic data generation in a testbench would be:

Code VHDL - [expand]
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process
begin
  a <= x"0000";
  b <= x"0001";
 
  wait for 10 ns;
  
  a <= x"0100";
  b <= x"FFFF";
 
  wait for 10 ns;
 
  -- generate more data here
  wait;
end process;
 

Re: error while compiling test bench

this code must not be compiled in a synthesisor. This must only be compiled in a simulator.
 

Re: error while compiling test bench

what do you mean??
 

that what I did and I got this error
Error (10533): VHDL Wait Statement error at adder_tb.vhd(25): Wait Statement must contain condition clause with UNTIL keyword
Click to expand...
 

Re: error while compiling test bench

What program are you using to compile your testbench code?
 

Re: error while compiling test bench

Quartus Prime 15.1
 

quartus is not a simulator, it is a synthesisor. you need ti run the testbench in a simulator, like modelsim.
 

hi,

quartus prime had a model-sim altera edition simulator.
@B21hasni :: what do you mean??
Click to expand...
what TrickyDicky asking you is ::are you using the simulator to see the waveform or are you synthesizing the design?

thanks and regards
 

The wait statement is wrong in your adder_tb testbench...
Code: 
wait for 10ns;

the line should be
Code: 
wait for 10 ns;

a space is required between the 10 and the ns.
 

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