Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

PWM generation using SG3525

Status
Not open for further replies.

Shroddha

Newbie level 3
Joined
Jul 6, 2018
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
33
I have created a simple PWM circuit using SG3525 to achieve 50% or more duty cycle. However the duty cycle gets saturated at only 30%( I have initially shorted the pin 1 and pin 9). Now when I have grounded pin 9 , it results in a sinusoidal output. Please tell me how to connect pin 9 and pin1 properly to achieve 50% or more duty cycle and such that I can even control my duty cycle.
 

Can you attach your test circuit?
 

Hi,

Mind that everybody who wants to help you needs:
* to find the datasheet and download it
* read the datasheet
* guess how you designed your circuit
* need to look at the datasheet what "pin1" or "pin9" means. (Usally they have useful names)
* and so on

I recommend to provide all this informations ... (then not every forum member needs to invest this high effort) ...
resulting in faster, more detailed and higher quantity replies.

Klaus
 

SG3525.PNG
This is the test circuit
https://www.onsemi.com/pub/Collateral/SG3525A-D.PDF
This is the datasheet
 

And it shows you how to connect pin 9.

Look at the block diagram of the document you linked.
Error amp is set up as a voltage follower. Pin 2 between
0 and VREF gives 0-100% (-ish) duty. But that duty is
ping-ponged between A and B outputs (which in the test
figure are grounded, so it must be a pretty irrelevant-to-
the-goal test).

It should be plain if you looked at Figure 1 that there is
no way you will get more than 49.99% duty cycle out
of either A or B output. Even if they weren't shorted to
ground. So you can give up now.
 

To generate more than 50% duty cycle, "AND" the two outputs together with a pair of diodes, or better, a gate.
 
Last edited:

We solved this problem. We can vary our pulse width from 0% to 40%(approx). But we have another problem.
The PWM output frequency does not match with that calculated. Formula for frequency of generated PWM is f=1/(CT*(0.7*RT+3*RD).
when RT=15k, CT=1nF, RD=22 Ohm. Frequency should've been 95KHz. But output frequency was around 41KHz.
also for RT=4.7k, CT=1nF, RD=470 Ohm.Frequency should've been around 266KHz. But our output frequency was around 155KHz.
We do not understand if we have done amy mistake here.
RT was connected between pin 6 and ground.
CT was connected between pin 5 and ground.
RD was connected between pin 5 and 7, as mentioned in the datasheet.
 

Hi,

Post your PCB layout, especially where we can see the GND plane.

Klaus
 

Sorry, we haven't yet implemented it on PCB. Because we haven't finalized the circuit. right now we have done it on veroboard. this is our circuit diagram.
**broken link removed**
 

Hi,

right now we have done it on veroboard.
A vetoboard is not suitable for switching power curcuits.
You can't fulfill the PCB layout requirements recommended in the datasheet.

Don't be surprised when it doesn't work like expected.

Klaus
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top