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VHDL code for Designing 16 Bit ALU

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B21hasni

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Error (10344): VHDL expression error at ALU_test.vhd(26): expression has 32 elements,

when I compiled the program below

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use work.ALU.all;
 
entity ALU_test is
    port(clk, reset: in std_logic;
        sel: in std_logic_vector(3 downto 0);
        A,B: in std_logic_vector (15 downto 0);
        Y: out std_logic_vector (15 downto 0));
 
end ALU_test;
 
architecture beh of ALU_test is
begin
    process(clk, reset)
    begin
    if reset = '1' then
    Y <= "0000000000000000";
    elsif rising_edge(clk) then
    case sel is
    When "0000" => Y <= pass_A(A);
When "0001" => Y <= Logical_AND (A,B);
When "0010" => Y <= Logical_OR (A,B);
When "0011" => Y <= addition (A,B);
When "0100" => Y <= subtraction (A,B);
When "0101" => Y <= multiplication (A,B);
When "0110" => Y <= Shift_L (A);
When "0111" => Y <= Shift_R (A);
when others => Null;
end case;
    end if;
    end process;
end beh;



I got this error
Error (10344): VHDL expression error at ALU_test.vhd(26): expression has 32 elements, but must have 16 elements

How can I override this error and compile successfully??
 
Last edited by a moderator:

Re: Error (10344): VHDL expression error at ALU_test.vhd(26): expression has 32 eleme

because multiplication increases the bit width of the result. How you change it is dependent on what you want to accomplish.
Make the output of multiplication the width of both A & B inputs, truncate the result, ... etc.

BTW you don't "override" errors you fix them.
 

Re: Error (10344): VHDL expression error at ALU_test.vhd(26): expression has 32 eleme

I solved the problem as shown below

Code:
When "0000" => Y (15 downto 0) <= pass_A(A);
		When "0001" => Y (15 downto 0) <= Logical_AND (A,B);
		When "0010" => Y (15 downto 0) <= Logical_OR (A,B);
		When "0011" => Y (15 downto 0) <= addition (A,B);
		When "0100" => Y (15 downto 0) <= subtraction (A,B);
		when "0101" => Y <= multiplication (A,B);
		When "0110" => Y (15 downto 0) <= Shift_L (A);
		When "0111" => Y (15 downto 0) <= Shift_R (A);
but now I have a problem when I simulate the program, I got the zeros at the output (Y) at every step

how i can fix the problem
 
Last edited by a moderator:

Re: Error (10344): VHDL expression error at ALU_test.vhd(26): expression has 32 eleme

I solved the problem as shown below

Code:
When "0000" => Y (15 downto 0) <= pass_A(A);
		When "0001" => Y (15 downto 0) <= Logical_AND (A,B);
		When "0010" => Y (15 downto 0) <= Logical_OR (A,B);
		When "0011" => Y (15 downto 0) <= addition (A,B);
		When "0100" => Y (15 downto 0) <= subtraction (A,B);
		when "0101" => Y <= multiplication (A,B);
		When "0110" => Y (15 downto 0) <= Shift_L (A);
		When "0111" => Y (15 downto 0) <= Shift_R (A);
but now I have a problem when I simulate the program, I got the zeros at the output (Y) at every step

how i can fix the problem
You expect an answer given you don't even include the definitions of all your signals and any possible changes to those functions in your other thread? Maybe your testbench (if you even have one) is broken or you didn't "force" the signals in the simulator properly or at the wrong time or between a clock cycle or you don't have a clock or etc....

You aren't making it easy for someone to help, in fact your method of asking for help basically appears like you want to waste everyone's time.
 

Re: Error (10344): VHDL expression error at ALU_test.vhd(26): expression has 32 eleme

this is the code I have, when I simulated I got (00000000000000000000000000000000) at the output every time I change the sel
Code:
library ieee;
use ieee.std_logic_1164.all;
use work.ALU.all;

entity ALU_test is
	port(clk, reset: in std_logic;
		sel: in std_logic_vector(3 downto 0);
		A,B: in std_logic_vector (15 downto 0);
		Y: out std_logic_vector (31 downto 0));

end ALU_test;

architecture beh of ALU_test is
begin
	process(clk, reset)
	begin
	if reset = '1' then
	Y <= "00000000000000000000000000000000";
	elsif rising_edge(clk) then
	case sel is
		When "0000" => Y (15 downto 0) <= pass_A(A);
		When "0001" => Y (15 downto 0) <= Logical_AND (A,B);
		When "0010" => Y (15 downto 0) <= Logical_OR (A,B);
		When "0011" => Y (15 downto 0) <= addition (A,B);
		When "0100" => Y (15 downto 0) <= subtraction (A,B);
		when "0101" => Y <= multiplication (A,B);
		When "0110" => Y (15 downto 0) <= Shift_L (A);
		When "0111" => Y (15 downto 0) <= Shift_R (A);
		when others => Null;
end case;
	end if;
	end process;
end beh;
 
Last edited by a moderator:

Re: Error (10344): VHDL expression error at ALU_test.vhd(26): expression has 32 eleme

I really need a help to run the codes, simulate and test it in the DE2-115 board for my graduation project
 

Re: Error (10344): VHDL expression error at ALU_test.vhd(26): expression has 32 eleme

So maybe you have reset set to 1 in you testbench (which you didn't post).

I see you didn't post your code with code tags...again.
put the following around your code next time you post...

Code C - [expand]
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[code]
...your code goes in here...
[/code]



- - - Updated - - -

I really need a help to run the codes, simulate and test it in the DE2-115 board for my graduation project
This project is very simple, I had to design a similar circuit (a 4 function calculator) back in my 2nd year of my degree with 7400 series parts. I would have been overjoyed to use Verilog or VHDL instead of drawing the schematic by hand and wiring it up on a breadboard to prove it worked.
 

Code:
library ieee;      --the declare the library iee which contains many packages  
use ieee.std_logic_1164.all;          -- import all package from std_logic_1164 into the entity
use work.ALU.all;	-- to make the contents of the ALU package from the work library visible 
entity ALU_test is           -- data identifier (entity)  name 
port(sel: in std_logic_vector(3 downto 0); -- sel control input of the 16-bit ALU
A,B: in std_logic_vector (15 downto 0); -- A,B Data input of the 16-bit ALU
Y: out std_logic_vector (31 downto 0)); -- 32-bit data output of the 16-bit ALU
end ALU_test;                       -- end the identifier 
architecture beh of ALU_test is  -- describe the internal view and the behavior of the circuit
begin
	process(sel,A,B)                 -- Since its sequential modeling we have to use process, its sequence of statements that declared in specified order
begin                                 -- begin the process
	if sel = "0000" then     --Using (if-then-else statement) command we have to describe the body of the program. The if-then-else statement checks each condition sequentially until it finds the correct condition. Then when the condition is correct it will execute it and then end
	Y (15 downto 0) <= pass_A(A); --Pass A
		elsif sel="0001" then
	Y (15 downto 0)<= Logical_AND (A,B); --AND
		elsif sel="0010" then
	Y (15 downto 0) <= Logical_OR (A,B); --OR
		elsif sel="0011" then
	Y (15 downto 0) <= addition (A,B); --Add
		elsif sel= "0100" then
	Y (15 downto 0) <= subtraction (A,B); --Sub
		elsif sel="0101" then
	Y <= multiplication (A,B); --Multi
		elsif sel= "0110" then
	Y (15 downto 0) <= Shift_L (A); --Shift left
		elsif sel="0111" then
	Y (15 downto 0)<= Shift_R (A); -- Shift right
	end if;                            --to end the process
	end process;                  --end the command  process
end beh;                                     --End the architecture

is that correct??
 

Does the simulation meet the project requirements? Does it synthesise and work in the FPGA.
 

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