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How to store and read 32 bit counter values as 4 8-bit registers ?

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AbinayaSivam

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Hi,

I am new to HDL language. I have written and compiled the basic Counter Verilog code. But i need store 32 bit counter values as 4 8-bit registers ? Please someone help me.

Code: 
  module counter
 #(parameter WIDTH=8)
 (
   input clk, enable, rst_n,
   output reg [WIDTH-1:0] count
 );
  always @ (posedge clk or negedge rst_n)
  begin
   if (~rst_n)
     count <= 0;
   else if (enable == 1'b1)
     count <= count + 1;
  end
 endmodule
 

Hi,

I can't see where you want to store the value.
We don't know about your hardware.
If you want to store them inside the PLD as registers, then I recommend to store the 32 bits all at once.
register <= count
But maybe you think of an external EEPROM via I2C... what do we know?

Usually if you want to store it, then you need to read them, too.
Maybe it makes more sense just to read them as 8 bit values.

It's a riddle.

Klaus
 

Hi,

I am working with FPGA. For my project, I need to implement Binary counter as 8-bit 8-bit registers.

I need to store like below
Code: 
       output reg [7:0]  Data_out_0,   //Reg-1
       output reg [7:0]  Data_out_1,   //Reg-2 
       output reg [7:0]  Data_out_2,   //Reg-3
       output reg [7:0]  Data_out_3,   //Reg-4

Any logic in Verilog, like switch cases. How to complete Counter logic as 4 8-bit registers ?
 

The code you posted is good. Just specify WIDTH=32. Now convert the 32 bit register to 4x8-bit:

Code: 
assign Data_out_0 = count[7:0]
assign Data_out_1 = count[15:8]
assign Data_out_2 = count[23:16]
assign Data_out_3 = count[31:24]
 

Thanks for your response. Now look over my code,whether the counter logic is ok.

Code: 
module counter
      (
        input clk, enable, rst_n,
        output [31:0] count,
      );
        reg count=0;
        output wire [7:0]  Data_out_0;
        output wire [7:0]  Data_out_1;
        output wire [7:0]  Data_out_2;
        output wire [7:0]  Data_out_3;

        assign Data_out_0 = count[7:0];
        assign Data_out_1 = count[15:8];
        assign Data_out_2 = count[23:16];
        assign Data_out_3 = count[31:24];

        always @ (posedge clk or negedge rst_n)
        begin
        if (~rst_n)
        count <= 0;
        else if (enable == 1'b1)
        count <= count + 1;
        end
        endmodule
 

Hi,

I don´t think this solution is true "4 8-bit registers".
It isn´t registered at all.
I think it´s just wired to Data_out_x. But I´m no specialist with HDL.

May I ask what´s the benefit instead of wiring out count[31..0]?
The 8-bit wise access also can be done outside of the module without drawbacks.
In my eyes the signals are the same, but just with different names.

***
The benefit of registers is that the value can be stored, while the counter continues to run.
The benefit of 8 bits may be to acces the value bytewise and MUX them to reduce external wire count.
None of them I see here.

On the other side there is no need for me to undertsand it.

Klaus
 

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