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[SOLVED] How do I do an ASIC post-synthesis timing simulation in Modelsim for Verilog

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AlexKeys

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Hello,
I have synthesised my Verilog HDL code in Synopsys DC and now I have to do a timing simulation. I do not want to use Xilinx or Altera tools as these will give me FPGA results. I want to know how to do the simulation taking into consideration my technology libraries (I suppose there has to be some resemblance of the tech files I used for synthesis) and netlist. I will be grateful for anyhelp offered. Thank you in advance.
 

You need a delay annotated netlist, the SDF format is popular for that.
 

Usually the technology library files have so rough time estimations (for example tsmc behavioral verilog files have a predefined delay of 0ns for combinational cells and 1ns for sequential cells).
When doing your simulation, just compile these files with your design to have the time information on the simulation.

However if you want result similar to the ones you will get for real, you will have to place and route your design first and get the SDF file that ThisIsNotSam mentioned. The propagation time of a cell depends on many factors like the input transition time and the output load capacitance (which is also dependent on the routing between cells). Therefore only after P&R can you extract them correctly.
 

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