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Manual Intentional Routing

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Mahmoud_Dagher

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In my place&route implementation in SoC Encounter, I'm placing certain instances and fix their positions by the command placeInstance -fixed , then I route between them manually by long close metals with minimum DRC (It's intentional for my task). The problem is that when I continue the implementation (placing) the standard cells and optimizing (Design) some of those connections are removed. Is there a way to fix those metal wires I drew manually so they are still connected till the end after all different steps?
 

Set the wire property to "fixed", it will not be touched by the other tools/steps.
 

ThisIsNotSam said:
Set the wire property to "fixed", it will not be touched by the other tools/steps.
Click to expand...

They are already "fixed". The problem is when I optDesign ; some parts of those wires are removed so they are no longer connected like I said!. What do you think I can do?
 

Maybe make the endpoints and interconnect a hard macro?
 

Hello,
I am also interested in this type of problems.
Can u explain how to make the hard macro and how to export that macro so it can be instantiated in verilog to be used in other designs (like the other cells in the foundry library)
 

Mahmoud_Dagher said:
They are already "fixed". The problem is when I optDesign ; some parts of those wires are removed so they are no longer connected like I said!. What do you think I can do?
Click to expand...

You can try optDesign -excludeNets option.
 

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