Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Problem measuring output impedance of CMOS inverter using ngspice

Status
Not open for further replies.
erikl said:
... generates a (nearly) full feedback amplifier, i.e. gain≈1 for low frequencies (LF), with corresponding low LF output impedance.
Click to expand...
FvM said:
Not in the frequency range of interest with 1F filter capacitor!
Click to expand...

Oh, overlooked, sorry! Cut-off frequency 0.16 fHz :cry:

@promach: change to 
Code VHDL - [expand]
1
2

CIN IN VSS 1p
Rf OUT IN 1E6
 

1F capacitor is just O.K. for simulation. It's bypassed in initial transient solution but cuts AC feedback even for high gain stages and mHz frquencies, in case they would be used.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top