+ Post New Thread
Page 1 of 2 1 2 LastLast
Results 1 to 20 of 22
  1. #1
    Advanced Member level 2
    Points: 2,897, Level: 12

    Join Date
    Feb 2016
    Posts
    543
    Helped
    1 / 1
    Points
    2,897
    Level
    12

    Problem measuring output impedance of CMOS inverter using ngspice

    Cross posting from https://sourceforge.net/p/ngspice/di...?limit=25#6896

    Why am I getting negative output impedance using the following test circuit ?

    Code:
    *CMOS inverter 
    
    .PARAM V_SUPPLY = 3.3
    .PARAM V_OUT = 2
    *.PARAM INP_FREQ = '#INP_FREQ#'
    *.PARAM INP_PERIOD = '1/INP_FREQ'
    *.PARAM NO_PERIODS = '4'
    *.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
    *.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
    .PARAM AC_POINTS = 10
    .PARAM AC_START = 1000
    .PARAM AC_STOP = 1E6
    
    *** *** SUPPLY VOLTAGES *** ***
    VDD VDD 0 'V_SUPPLY'
    VSS VSS 0 0
    
    *** *** INPUT SIGNAL *** ***
    VSIG IN VSS AC 1 DC 1
    
    *** *** CIRCUIT UNDER TEST *** ***
    MP OUT IN VDD VDD P1 W=0.07963 L=0.001 
    MN OUT IN VSS VSS N1 W=0.03982 L=0.001 
    
    ** CL OUT VSS 3p
    RIN IN VSS 1G
    
    Rf OUT IN 0.01
    ** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292  
    
    *** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
    *VOUT VOUT 0 'V_OUT'
    IOUT OUT VSS AC 1 DC 1
    
    *** *** ANALYSIS *** ***
    *.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
    *.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
    *
    *.PROBE TRAN V(IN)
    *.PROBE TRAN V(OUT)
    .OPTION POST PROBE ACCURATE
    .include modelcard.nmos
    .include modelcard.pmos
    
    .control
    *AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
    AC dec 10 1000 1E6
    
    let ROUT=OUT/(i(Vss))
    plot ROUT
    print ROUT > ROUT.log
    .endc
    
    .END

  2. #2
    Super Moderator
    Points: 256,166, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    44,687
    Helped
    13593 / 13593
    Points
    256,166
    Level
    100

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    There may be other faults, but you have two AC sources activated simultaneously, VSIG and IOUT. This way you don't measure output impedance.


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  3. #3
    Super Moderator
    Points: 51,680, Level: 55
    Achievements:
    7 years registered
    erikl's Avatar
    Join Date
    Sep 2008
    Location
    Germany
    Posts
    8,077
    Helped
    2652 / 2652
    Points
    51,680
    Level
    55

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    I think this depends on the direction of i(Vss), which probably is negative.
    BTW: i(Vss) probably contains all currents into VSS, i.e. also those of the pre-stages.

    I'd suggest you better use an ROUT definition like
    Code:
    let ROUT=OUT/(i(OUT))
    ... and care for the correct output condition (usually short circuit). Use a very small resistor (like your Rf) connected from output to VSS via a huge capacitor.



  4. #4
    Advanced Member level 2
    Points: 2,897, Level: 12

    Join Date
    Feb 2016
    Posts
    543
    Helped
    1 / 1
    Points
    2,897
    Level
    12

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    two AC sources activated simultaneously, VSIG and IOUT.
    @FvM

    What do you suggest then ?

    - - - Updated - - -

    See the resulting frequency response when I short the CMOS inverter input to ground, literally means that I only have one AC source in the test circuit.

    Code:
    *CMOS inverter 
    
    .PARAM V_SUPPLY = 3.3
    .PARAM V_OUT = 2
    *.PARAM INP_FREQ = '#INP_FREQ#'
    *.PARAM INP_PERIOD = '1/INP_FREQ'
    *.PARAM NO_PERIODS = '4'
    *.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
    *.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
    .PARAM AC_POINTS = 10
    .PARAM AC_START = 1000
    .PARAM AC_STOP = 1E6
    
    *** *** SUPPLY VOLTAGES *** ***
    VDD VDD 0 'V_SUPPLY'
    VSS VSS 0 0
    
    *** *** INPUT SIGNAL *** ***
    VSIG IN VSS 0
    
    *** *** CIRCUIT UNDER TEST *** ***
    MP OUT IN VDD VDD P1 W=0.07963 L=0.001 
    MN OUT IN VSS VSS N1 W=0.03982 L=0.001 
    
    ** CL OUT VSS 3p
    RIN IN VSS 1G
    
    Rf OUT IN 0.01
    ** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292  
    
    *** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
    *VOUT VOUT 0 'V_OUT'
    IOUT OUT VSS AC 1 DC 1
    
    *** *** ANALYSIS *** ***
    *.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
    *.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
    *
    *.PROBE TRAN V(IN)
    *.PROBE TRAN V(OUT)
    .OPTION POST PROBE ACCURATE
    .include modelcard.nmos
    .include modelcard.pmos
    
    .control
    *AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
    AC dec 10 1000 1E6
    
    let ROUT=OUT/(i(VSS))
    plot ROUT
    print ROUT > ROUT.log
    .endc
    
    .END
    Click image for larger version. 

Name:	Screenshot from 2018-07-04 11-42-00.png 
Views:	8 
Size:	52.0 KB 
ID:	147672


    1 members found this post helpful.

  5. #5
    Super Moderator
    Points: 256,166, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    44,687
    Helped
    13593 / 13593
    Points
    256,166
    Level
    100

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    Shorting input to ground is neither correct, you want DC bias but no AC source.

    Getting still negative impedance points to a sign error, as already mentioned by erikl. Seriously I don't understand the reasoning behind
    ROUT=OUT/(i(VSS))

    Why I(Vss)? If you send 1 A to the output, the output impedance is equal to V(out).



  6. #6
    Advanced Member level 2
    Points: 2,897, Level: 12

    Join Date
    Feb 2016
    Posts
    543
    Helped
    1 / 1
    Points
    2,897
    Level
    12

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    you want DC bias but no AC source.
    @FvM

    The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread....=1#post1617292



  7. #7
    Advanced Member level 2
    Points: 2,897, Level: 12

    Join Date
    Feb 2016
    Posts
    543
    Helped
    1 / 1
    Points
    2,897
    Level
    12

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    Anyone have comment about the following simulation result ? I am going to double check against manual maths calculation ?



    Code:
    *CMOS inverter 
    
    .PARAM V_SUPPLY = 3.3
    .PARAM V_OUT = 2
    *.PARAM INP_FREQ = '#INP_FREQ#'
    *.PARAM INP_PERIOD = '1/INP_FREQ'
    *.PARAM NO_PERIODS = '4'
    *.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
    *.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
    .PARAM AC_POINTS = 10
    .PARAM AC_START = 1000
    .PARAM AC_STOP = 1E6
    
    *** *** SUPPLY VOLTAGES *** ***
    VDD VDD 0 'V_SUPPLY'
    VSS VSS 0 0
    
    *** *** INPUT SIGNAL *** *** set Vgs manually such that both mosfets are at saturation 
    VSIG IN VSS AC 1 DC 'V_SUPPLY/2'
    
    *** *** CIRCUIT UNDER TEST *** ***
    MP OUT IN VDD VDD P1 W=2U L=2U
    MN OUT IN VSS VSS N1 W=1U L=2U 
    
    ** CL OUT VSS 3p
    ** RIN IN VSS 1G
    
    ** CIN IN VSS 111
    ** Rf OUT IN 0.01
    ** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292  
    
    
    *** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
    *VOUT VOUT 0 'V_OUT'
    *** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
    IOUT VSS OUT AC 1
    
    *** *** ANALYSIS *** ***
    *.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
    *.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
    *
    *.PROBE TRAN V(IN)
    *.PROBE TRAN V(OUT)
    .OPTION POST PROBE ACCURATE
    .include modelcard.nmos
    .include modelcard.pmos
    
    .control
    *AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
    AC dec 10 1000 1E6
    
    let ROUT=OUT/abs(i(VSS))
    plot ROUT
    print ROUT > ROUT.log
    .endc
    
    .END



    •   AltAdvertisement

        
       

  8. #8
    Super Moderator
    Points: 256,166, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    44,687
    Helped
    13593 / 13593
    Points
    256,166
    Level
    100

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source
    Don't agree. It makes particularly sense if you want to guarantee that the circuit is biased in active range (both transistors in saturation) without tuning a DC voltage.

    But my point was different. You must not place a second AC source along with the bias circuit. Your latest post clarifies that you still have. Whatever the latest plot shows, it can't be output impedance.

    Code:
    VSIG IN VSS AC 1 DC 'V_SUPPLY/2'
    I'm outty



  9. #9
    Advanced Member level 5
    Points: 38,991, Level: 48

    Join Date
    Mar 2008
    Location
    USA
    Posts
    6,302
    Helped
    1836 / 1836
    Points
    38,991
    Level
    48

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    An inverter's output impedance will change with common
    mode output position and with input bias. You can't really
    have both transistors of a standard CMOS inverter in the
    saturation region, at once, because the gates are co-driven.
    The Zout will also have a Miller element at higher frequencies
    which makes Zo have a parallel gain, Zin dependent term.
    So you want to represent the gate drive reasonably.

    If you are operating large signal then the output impedance
    will be constantly changing and small signal analysis is not
    your friend, you might want a PSS or other transient based
    analysis to get a Zout. Though it looks like your analysis
    does not extend to "real RF".

    A replica biasing scheme might serve you if you want the
    output at VDD/2 for analysis; one inverter shorting out:in,
    and use that voltage for the gate of the second as well.
    Ideal matching in the simulator will make the test inverter
    output go to VDD/2 as well.



  10. #10
    Advanced Member level 2
    Points: 2,897, Level: 12

    Join Date
    Feb 2016
    Posts
    543
    Helped
    1 / 1
    Points
    2,897
    Level
    12

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    You must not place a second AC source along with the bias circuit.
    @FvM

    Could you justify why ?



    •   AltAdvertisement

        
       

  11. #11
    Super Moderator
    Points: 256,166, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    44,687
    Helped
    13593 / 13593
    Points
    256,166
    Level
    100

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    Both sources are acting simultaneously, the output voltage you are measuring is caused by the superposition of both, but you want to see only the effect of injected output current.

    That's just elementary electrical network theory, I believe.



  12. #12
    Advanced Member level 2
    Points: 2,897, Level: 12

    Join Date
    Feb 2016
    Posts
    543
    Helped
    1 / 1
    Points
    2,897
    Level
    12

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    No matter how I measure the output impedance, the result can never come any close to the following theoretical calculation

    https://github.com/imr/ngspice/blob/...modelcard.pmos



    Code:
    *CMOS inverter 
    
    .PARAM V_SUPPLY = 3.3
    .PARAM V_OUT = 2
    *.PARAM INP_FREQ = '#INP_FREQ#'
    *.PARAM INP_PERIOD = '1/INP_FREQ'
    *.PARAM NO_PERIODS = '4'
    *.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
    *.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
    .PARAM AC_POINTS = 10
    .PARAM AC_START = 1000
    .PARAM AC_STOP = 1E6
    
    *** *** SUPPLY VOLTAGES *** ***
    VDD VDD 0 'V_SUPPLY'
    VSS VSS 0 0
    
    *** *** INPUT SIGNAL *** *** 
    VSIG IN VSS 0
    ** VSIG IN VSS AC 1 DC 'V_SUPPLY/2'
    
    *** *** CIRCUIT UNDER TEST *** ***
    MP OUT IN VDD VDD P1 W=2U L=2U
    MN OUT IN VSS VSS N1 W=1U L=2U 
    
    ** CL OUT VSS 3p
    ** RIN IN VSS 1G
    
    CIN IN VSS 1E9
    Rf OUT IN 1E9
    ** Lf OUT IN 1E-12
    ** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292  
    
    
    *** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
    *VOUT VOUT 0 'V_OUT'
    *** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
    IOUT VSS OUT AC 1
    
    *** *** ANALYSIS *** ***
    *.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
    *.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
    *
    *.PROBE TRAN V(IN)
    *.PROBE TRAN V(OUT)
    .OPTION POST PROBE ACCURATE
    .include modelcard.nmos
    .include modelcard.pmos
    
    .control
    *AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
    AC dec 10 1000 1E6
    
    let ROUT=OUT/abs(i(VSS))
    plot ROUT
    print ROUT > ROUT.log
    .endc
    
    .END
    Last edited by promach; 6th July 2018 at 15:18.



  13. #13
    Advanced Member level 5
    Points: 38,991, Level: 48

    Join Date
    Mar 2008
    Location
    USA
    Posts
    6,302
    Helped
    1836 / 1836
    Points
    38,991
    Level
    48

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    Do you see the bold text "(valid in the saturation region)"?

    Do you see that in an inverter one, the other or both
    devices -will not- be in saturation under any condition?

    And if they both were, the fact of -two- FET conductances
    in drain-parallel would be some kind of error term relative
    to that single-transistor formula.



  14. #14
    Advanced Member level 2
    Points: 2,897, Level: 12

    Join Date
    Feb 2016
    Posts
    543
    Helped
    1 / 1
    Points
    2,897
    Level
    12

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    See https://electronics.stackexchange.co...-cmos-inverter

    Code:
    *CMOS inverter https://electronics.stackexchange.com/questions/383552/measurement-of-output-impedance-of-a-cmos-inverter
    
    .PARAM V_SUPPLY = 3.3
    .PARAM V_OUT = 2
    *.PARAM INP_FREQ = '#INP_FREQ#'
    *.PARAM INP_PERIOD = '1/INP_FREQ'
    *.PARAM NO_PERIODS = '4'
    *.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
    *.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
    .PARAM AC_POINTS = 10
    .PARAM AC_START = 1000
    .PARAM AC_STOP = 1E6
    
    *** *** SUPPLY VOLTAGES *** ***
    VDD VDD 0 'V_SUPPLY'
    VSS VSS 0 0
    
    *** *** INPUT SIGNAL *** *** 
    ** VSIG IN VSS 0
    ** VSIG IN VSS AC 1 DC 0
    ** VSIG IN VSS AC 1 DC 'V_SUPPLY/2'
    
    *** *** CIRCUIT UNDER TEST *** ***
    MP OUT IN VDD VDD P1 W=2U L=2U
    MN OUT IN VSS VSS N1 W=1U L=2U 
    
    ** CL OUT VSS 3p
    ** RIN IN VSS 1G
    
    CIN IN VSS 1
    Rf OUT IN 1E15
    ** Lf OUT IN 1E-15
    ** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292  
    
    
    *** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
    *VOUT VOUT 0 'V_OUT'
    *** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
    IOUT VSS OUT AC 1
    
    *** *** ANALYSIS *** ***
    *.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
    *.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
    *
    *.PROBE TRAN V(IN)
    *.PROBE TRAN V(OUT)
    .OPTION POST PROBE ACCURATE
    .include modelcard.nmos
    .include modelcard.pmos
    
    .control
    *AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
    AC dec 10 1000 1E6
    
    let ROUT=OUT/abs(i(VSS))
    plot ROUT
    print ROUT > ROUT.log
    .endc
    
    .END



  15. #15
    Super Moderator
    Points: 51,680, Level: 55
    Achievements:
    7 years registered
    erikl's Avatar
    Join Date
    Sep 2008
    Location
    Germany
    Posts
    8,077
    Helped
    2652 / 2652
    Points
    51,680
    Level
    55

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    You have
    Code VHDL - [expand]
    1
    
    IOUT VSS OUT AC 1
    so try
    Code VHDL - [expand]
    1
    
    let ROUT=V(OUT)
    ... as FvM told you in post #5 .



  16. #16
    Advanced Member level 2
    Points: 2,897, Level: 12

    Join Date
    Feb 2016
    Posts
    543
    Helped
    1 / 1
    Points
    2,897
    Level
    12

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    The following is my updated test circuit. However, using your advice give me lower output impedance, about 8 kilo ohms lower compared to theoretical calculation. I am still very doubtful about the correctness of test circuit setup for output impedance measurement.

    Code:
    *CMOS inverter https://electronics.stackexchange.com/questions/383552/measurement-of-output-impedance-of-a-cmos-inverter
    
    .PARAM V_SUPPLY = 3.3
    .PARAM V_OUT = 2
    *.PARAM INP_FREQ = '#INP_FREQ#'
    *.PARAM INP_PERIOD = '1/INP_FREQ'
    *.PARAM NO_PERIODS = '4'
    *.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
    *.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
    .PARAM AC_POINTS = 10
    .PARAM AC_START = 1000
    .PARAM AC_STOP = 1E6
    
    *** *** SUPPLY VOLTAGES *** ***
    VDD VDD 0 'V_SUPPLY'
    VSS VSS 0 0
    
    *** *** INPUT SIGNAL *** *** 
    ** VSIG IN VSS 0
    ** VSIG IN VSS AC 1 DC 0
    ** VSIG IN VSS AC 1 DC 'V_SUPPLY/2'
    
    *** *** CIRCUIT UNDER TEST *** ***
    MP OUT IN VDD VDD P1 W=2U L=2U
    MN OUT IN VSS VSS N1 W=1U L=2U 
    
    ** CL OUT VSS 3p
    ** RIN IN VSS 1G
    
    CIN IN VSS 1
    Rf OUT IN 1E15
    ** Lf OUT IN 1E-15
    ** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292  
    
    
    *** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT *** ***
    ** this is a way to measure or plot the current source IOUT in spice using 0V voltage source
    VOUT OUT VOUT 0
    *** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
    IOUT VSS VOUT AC 1
    
    *** *** ANALYSIS *** ***
    *.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
    *.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
    *
    *.PROBE TRAN V(IN)
    *.PROBE TRAN V(OUT)
    .OPTION POST PROBE ACCURATE
    .include modelcard.nmos
    .include modelcard.pmos
    ** https://github.com/imr/ngspice/blob/master/examples/xspice/table/modelcards/modelcard.nmos
    ** https://github.com/imr/ngspice/blob/master/examples/xspice/table/modelcards/modelcard.pmos
    
    .control
    *AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
    AC dec 10 1000 1E6
    
    let ROUT=v(OUT)/abs(i(VOUT))
    plot ROUT
    print ROUT > ROUT.log
    .endc
    
    .END



  17. #17
    Super Moderator
    Points: 256,166, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    44,687
    Helped
    13593 / 13593
    Points
    256,166
    Level
    100

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    The test circuit should basically work. Rf may be a way too high if the MOSFETs show leakage current. 1e9 should be more than suffcient. Check the bias point!


    1 members found this post helpful.

  18. #18
    Advanced Member level 2
    Points: 2,897, Level: 12

    Join Date
    Feb 2016
    Posts
    543
    Helped
    1 / 1
    Points
    2,897
    Level
    12

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    Rf may be a way too high if the MOSFETs show leakage current.
    Why if I decrease Rf from 1E15 to 1E9 , ROUT increases from 48.563 kohm to 48.5705 kohm

    Check the bias point!
    This is a self-bias CMOS inverter. Could you advise ?



  19. #19
    Super Moderator
    Points: 51,680, Level: 55
    Achievements:
    7 years registered
    erikl's Avatar
    Join Date
    Sep 2008
    Location
    Germany
    Posts
    8,077
    Helped
    2652 / 2652
    Points
    51,680
    Level
    55

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    Quote Originally Posted by promach View Post
    ... using your advice give me lower output impedance, about 8 kilo ohms lower compared to theoretical calculation.
    Code VHDL - [expand]
    1
    
    Rf OUT IN 1E15
    ... generates a (nearly) full feedback amplifier, i.e. gain≈1 for low frequencies (LF), with corresponding low LF output impedance. Did you consider this?



  20. #20
    Super Moderator
    Points: 256,166, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    44,687
    Helped
    13593 / 13593
    Points
    256,166
    Level
    100

    Re: Problem measuring output impedance of CMOS inverter using ngspice

    ... generates a (nearly) full feedback amplifier, i.e. gain≈1 for low frequencies (LF), with corresponding low LF output impedance.
    Not in the frequency range of interest with 1F filter capacitor!


    Why if I decrease Rf from 1E15 to 1E9 , ROUT increases from 48.563 kohm to 48.5705 kohm
    You didn't tell before how much the expected value is. 20% deviation sounds realistic.

    This is a self-bias CMOS inverter. Could you advise ?
    Means check the bias resistor voltage drop. Apparently it's acceptable. That's it.



    •   AltAdvertisement

        
       

--[[ ]]--