+ Post New Thread
Results 1 to 20 of 22

3rd July 2018, 16:28 #1
 Join Date
 Feb 2016
 Posts
 503
 Helped
 1 / 1
 Points
 2,695
 Level
 12
Problem measuring output impedance of CMOS inverter using ngspice
Cross posting from https://sourceforge.net/p/ngspice/di...?limit=25#6896
Why am I getting negative output impedance using the following test circuit ?
Code:*CMOS inverter .PARAM V_SUPPLY = 3.3 .PARAM V_OUT = 2 *.PARAM INP_FREQ = '#INP_FREQ#' *.PARAM INP_PERIOD = '1/INP_FREQ' *.PARAM NO_PERIODS = '4' *.PARAM TMEAS_START = '(NO_PERIODS1)*INP_PERIOD' *.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD' .PARAM AC_POINTS = 10 .PARAM AC_START = 1000 .PARAM AC_STOP = 1E6 *** *** SUPPLY VOLTAGES *** *** VDD VDD 0 'V_SUPPLY' VSS VSS 0 0 *** *** INPUT SIGNAL *** *** VSIG IN VSS AC 1 DC 1 *** *** CIRCUIT UNDER TEST *** *** MP OUT IN VDD VDD P1 W=0.07963 L=0.001 MN OUT IN VSS VSS N1 W=0.03982 L=0.001 ** CL OUT VSS 3p RIN IN VSS 1G Rf OUT IN 0.01 ** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214NoiseinCMOSInverter&p=1617292&viewfull=1#post1617292 *** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** *** *VOUT VOUT 0 'V_OUT' IOUT OUT VSS AC 1 DC 1 *** *** ANALYSIS *** *** *.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP' *.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD' * *.PROBE TRAN V(IN) *.PROBE TRAN V(OUT) .OPTION POST PROBE ACCURATE .include modelcard.nmos .include modelcard.pmos .control *AC dec 'AC_POINTS' 'AC_START' 'AC_STOP' AC dec 10 1000 1E6 let ROUT=OUT/(i(Vss)) plot ROUT print ROUT > ROUT.log .endc .END

3rd July 2018, 18:33 #2
 Join Date
 Jan 2008
 Location
 Bochum, Germany
 Posts
 44,233
 Helped
 13462 / 13462
 Points
 253,869
 Level
 100
Re: Problem measuring output impedance of CMOS inverter using ngspice
There may be other faults, but you have two AC sources activated simultaneously, VSIG and IOUT. This way you don't measure output impedance.
1 members found this post helpful.

3rd July 2018, 20:06 #3
 Join Date
 Sep 2008
 Location
 Germany
 Posts
 8,077
 Helped
 2647 / 2647
 Points
 51,599
 Level
 55
Re: Problem measuring output impedance of CMOS inverter using ngspice
I think this depends on the direction of i(Vss), which probably is negative.
BTW: i(Vss) probably contains all currents into VSS, i.e. also those of the prestages.
I'd suggest you better use an ROUT definition likeCode:let ROUT=OUT/(i(OUT))

4th July 2018, 04:45 #4
 Join Date
 Feb 2016
 Posts
 503
 Helped
 1 / 1
 Points
 2,695
 Level
 12
Re: Problem measuring output impedance of CMOS inverter using ngspice
two AC sources activated simultaneously, VSIG and IOUT.
What do you suggest then ?
   Updated   
See the resulting frequency response when I short the CMOS inverter input to ground, literally means that I only have one AC source in the test circuit.
Code:*CMOS inverter .PARAM V_SUPPLY = 3.3 .PARAM V_OUT = 2 *.PARAM INP_FREQ = '#INP_FREQ#' *.PARAM INP_PERIOD = '1/INP_FREQ' *.PARAM NO_PERIODS = '4' *.PARAM TMEAS_START = '(NO_PERIODS1)*INP_PERIOD' *.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD' .PARAM AC_POINTS = 10 .PARAM AC_START = 1000 .PARAM AC_STOP = 1E6 *** *** SUPPLY VOLTAGES *** *** VDD VDD 0 'V_SUPPLY' VSS VSS 0 0 *** *** INPUT SIGNAL *** *** VSIG IN VSS 0 *** *** CIRCUIT UNDER TEST *** *** MP OUT IN VDD VDD P1 W=0.07963 L=0.001 MN OUT IN VSS VSS N1 W=0.03982 L=0.001 ** CL OUT VSS 3p RIN IN VSS 1G Rf OUT IN 0.01 ** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214NoiseinCMOSInverter&p=1617292&viewfull=1#post1617292 *** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** *** *VOUT VOUT 0 'V_OUT' IOUT OUT VSS AC 1 DC 1 *** *** ANALYSIS *** *** *.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP' *.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD' * *.PROBE TRAN V(IN) *.PROBE TRAN V(OUT) .OPTION POST PROBE ACCURATE .include modelcard.nmos .include modelcard.pmos .control *AC dec 'AC_POINTS' 'AC_START' 'AC_STOP' AC dec 10 1000 1E6 let ROUT=OUT/(i(VSS)) plot ROUT print ROUT > ROUT.log .endc .END
1 members found this post helpful.

4th July 2018, 08:42 #5
 Join Date
 Jan 2008
 Location
 Bochum, Germany
 Posts
 44,233
 Helped
 13462 / 13462
 Points
 253,869
 Level
 100
Re: Problem measuring output impedance of CMOS inverter using ngspice
Shorting input to ground is neither correct, you want DC bias but no AC source.
Getting still negative impedance points to a sign error, as already mentioned by erikl. Seriously I don't understand the reasoning behind
ROUT=OUT/(i(VSS))
Why I(Vss)? If you send 1 A to the output, the output impedance is equal to V(out).

Advertisment

4th July 2018, 10:27 #6
 Join Date
 Feb 2016
 Posts
 503
 Helped
 1 / 1
 Points
 2,695
 Level
 12
Re: Problem measuring output impedance of CMOS inverter using ngspice
you want DC bias but no AC source.
The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread....=1#post1617292

5th July 2018, 01:44 #7
 Join Date
 Feb 2016
 Posts
 503
 Helped
 1 / 1
 Points
 2,695
 Level
 12
Re: Problem measuring output impedance of CMOS inverter using ngspice
Anyone have comment about the following simulation result ? I am going to double check against manual maths calculation ?
Code:*CMOS inverter .PARAM V_SUPPLY = 3.3 .PARAM V_OUT = 2 *.PARAM INP_FREQ = '#INP_FREQ#' *.PARAM INP_PERIOD = '1/INP_FREQ' *.PARAM NO_PERIODS = '4' *.PARAM TMEAS_START = '(NO_PERIODS1)*INP_PERIOD' *.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD' .PARAM AC_POINTS = 10 .PARAM AC_START = 1000 .PARAM AC_STOP = 1E6 *** *** SUPPLY VOLTAGES *** *** VDD VDD 0 'V_SUPPLY' VSS VSS 0 0 *** *** INPUT SIGNAL *** *** set Vgs manually such that both mosfets are at saturation VSIG IN VSS AC 1 DC 'V_SUPPLY/2' *** *** CIRCUIT UNDER TEST *** *** MP OUT IN VDD VDD P1 W=2U L=2U MN OUT IN VSS VSS N1 W=1U L=2U ** CL OUT VSS 3p ** RIN IN VSS 1G ** CIN IN VSS 111 ** Rf OUT IN 0.01 ** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214NoiseinCMOSInverter&p=1617292&viewfull=1#post1617292 *** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** *** *VOUT VOUT 0 'V_OUT' *** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS IOUT VSS OUT AC 1 *** *** ANALYSIS *** *** *.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP' *.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD' * *.PROBE TRAN V(IN) *.PROBE TRAN V(OUT) .OPTION POST PROBE ACCURATE .include modelcard.nmos .include modelcard.pmos .control *AC dec 'AC_POINTS' 'AC_START' 'AC_STOP' AC dec 10 1000 1E6 let ROUT=OUT/abs(i(VSS)) plot ROUT print ROUT > ROUT.log .endc .END

5th July 2018, 18:06 #8
 Join Date
 Jan 2008
 Location
 Bochum, Germany
 Posts
 44,233
 Helped
 13462 / 13462
 Points
 253,869
 Level
 100
Re: Problem measuring output impedance of CMOS inverter using ngspice
The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source
But my point was different. You must not place a second AC source along with the bias circuit. Your latest post clarifies that you still have. Whatever the latest plot shows, it can't be output impedance.
Code:VSIG IN VSS AC 1 DC 'V_SUPPLY/2'

5th July 2018, 18:57 #9
 Join Date
 Mar 2008
 Location
 USA
 Posts
 6,247
 Helped
 1809 / 1809
 Points
 38,593
 Level
 48
Re: Problem measuring output impedance of CMOS inverter using ngspice
An inverter's output impedance will change with common
mode output position and with input bias. You can't really
have both transistors of a standard CMOS inverter in the
saturation region, at once, because the gates are codriven.
The Zout will also have a Miller element at higher frequencies
which makes Zo have a parallel gain, Zin dependent term.
So you want to represent the gate drive reasonably.
If you are operating large signal then the output impedance
will be constantly changing and small signal analysis is not
your friend, you might want a PSS or other transient based
analysis to get a Zout. Though it looks like your analysis
does not extend to "real RF".
A replica biasing scheme might serve you if you want the
output at VDD/2 for analysis; one inverter shorting out:in,
and use that voltage for the gate of the second as well.
Ideal matching in the simulator will make the test inverter
output go to VDD/2 as well.

5th July 2018, 21:39 #10
 Join Date
 Feb 2016
 Posts
 503
 Helped
 1 / 1
 Points
 2,695
 Level
 12
Re: Problem measuring output impedance of CMOS inverter using ngspice
You must not place a second AC source along with the bias circuit.
Could you justify why ?

Advertisment

5th July 2018, 22:27 #11
 Join Date
 Jan 2008
 Location
 Bochum, Germany
 Posts
 44,233
 Helped
 13462 / 13462
 Points
 253,869
 Level
 100
Re: Problem measuring output impedance of CMOS inverter using ngspice
Both sources are acting simultaneously, the output voltage you are measuring is caused by the superposition of both, but you want to see only the effect of injected output current.
That's just elementary electrical network theory, I believe.

6th July 2018, 15:12 #12
 Join Date
 Feb 2016
 Posts
 503
 Helped
 1 / 1
 Points
 2,695
 Level
 12
Re: Problem measuring output impedance of CMOS inverter using ngspice
No matter how I measure the output impedance, the result can never come any close to the following theoretical calculation
https://github.com/imr/ngspice/blob/...modelcard.pmos
Code:*CMOS inverter .PARAM V_SUPPLY = 3.3 .PARAM V_OUT = 2 *.PARAM INP_FREQ = '#INP_FREQ#' *.PARAM INP_PERIOD = '1/INP_FREQ' *.PARAM NO_PERIODS = '4' *.PARAM TMEAS_START = '(NO_PERIODS1)*INP_PERIOD' *.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD' .PARAM AC_POINTS = 10 .PARAM AC_START = 1000 .PARAM AC_STOP = 1E6 *** *** SUPPLY VOLTAGES *** *** VDD VDD 0 'V_SUPPLY' VSS VSS 0 0 *** *** INPUT SIGNAL *** *** VSIG IN VSS 0 ** VSIG IN VSS AC 1 DC 'V_SUPPLY/2' *** *** CIRCUIT UNDER TEST *** *** MP OUT IN VDD VDD P1 W=2U L=2U MN OUT IN VSS VSS N1 W=1U L=2U ** CL OUT VSS 3p ** RIN IN VSS 1G CIN IN VSS 1E9 Rf OUT IN 1E9 ** Lf OUT IN 1E12 ** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214NoiseinCMOSInverter&p=1617292&viewfull=1#post1617292 *** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** *** *VOUT VOUT 0 'V_OUT' *** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS IOUT VSS OUT AC 1 *** *** ANALYSIS *** *** *.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP' *.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD' * *.PROBE TRAN V(IN) *.PROBE TRAN V(OUT) .OPTION POST PROBE ACCURATE .include modelcard.nmos .include modelcard.pmos .control *AC dec 'AC_POINTS' 'AC_START' 'AC_STOP' AC dec 10 1000 1E6 let ROUT=OUT/abs(i(VSS)) plot ROUT print ROUT > ROUT.log .endc .END
Last edited by promach; 6th July 2018 at 15:18.

6th July 2018, 16:55 #13
 Join Date
 Mar 2008
 Location
 USA
 Posts
 6,247
 Helped
 1809 / 1809
 Points
 38,593
 Level
 48
Re: Problem measuring output impedance of CMOS inverter using ngspice
Do you see the bold text "(valid in the saturation region)"?
Do you see that in an inverter one, the other or both
devices will not be in saturation under any condition?
And if they both were, the fact of two FET conductances
in drainparallel would be some kind of error term relative
to that singletransistor formula.

8th July 2018, 10:44 #14
 Join Date
 Feb 2016
 Posts
 503
 Helped
 1 / 1
 Points
 2,695
 Level
 12
Re: Problem measuring output impedance of CMOS inverter using ngspice
See https://electronics.stackexchange.co...cmosinverter
Code:*CMOS inverter https://electronics.stackexchange.com/questions/383552/measurementofoutputimpedanceofacmosinverter .PARAM V_SUPPLY = 3.3 .PARAM V_OUT = 2 *.PARAM INP_FREQ = '#INP_FREQ#' *.PARAM INP_PERIOD = '1/INP_FREQ' *.PARAM NO_PERIODS = '4' *.PARAM TMEAS_START = '(NO_PERIODS1)*INP_PERIOD' *.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD' .PARAM AC_POINTS = 10 .PARAM AC_START = 1000 .PARAM AC_STOP = 1E6 *** *** SUPPLY VOLTAGES *** *** VDD VDD 0 'V_SUPPLY' VSS VSS 0 0 *** *** INPUT SIGNAL *** *** ** VSIG IN VSS 0 ** VSIG IN VSS AC 1 DC 0 ** VSIG IN VSS AC 1 DC 'V_SUPPLY/2' *** *** CIRCUIT UNDER TEST *** *** MP OUT IN VDD VDD P1 W=2U L=2U MN OUT IN VSS VSS N1 W=1U L=2U ** CL OUT VSS 3p ** RIN IN VSS 1G CIN IN VSS 1 Rf OUT IN 1E15 ** Lf OUT IN 1E15 ** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214NoiseinCMOSInverter&p=1617292&viewfull=1#post1617292 *** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** *** *VOUT VOUT 0 'V_OUT' *** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS IOUT VSS OUT AC 1 *** *** ANALYSIS *** *** *.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP' *.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD' * *.PROBE TRAN V(IN) *.PROBE TRAN V(OUT) .OPTION POST PROBE ACCURATE .include modelcard.nmos .include modelcard.pmos .control *AC dec 'AC_POINTS' 'AC_START' 'AC_STOP' AC dec 10 1000 1E6 let ROUT=OUT/abs(i(VSS)) plot ROUT print ROUT > ROUT.log .endc .END

8th July 2018, 20:03 #15
 Join Date
 Sep 2008
 Location
 Germany
 Posts
 8,077
 Helped
 2647 / 2647
 Points
 51,599
 Level
 55
Re: Problem measuring output impedance of CMOS inverter using ngspice
You have
Code VHDL  [expand] 1
IOUT VSS OUT AC 1
Code VHDL  [expand] 1
let ROUT=V(OUT)

9th July 2018, 01:32 #16
 Join Date
 Feb 2016
 Posts
 503
 Helped
 1 / 1
 Points
 2,695
 Level
 12
Re: Problem measuring output impedance of CMOS inverter using ngspice
The following is my updated test circuit. However, using your advice give me lower output impedance, about 8 kilo ohms lower compared to theoretical calculation. I am still very doubtful about the correctness of test circuit setup for output impedance measurement.
Code:*CMOS inverter https://electronics.stackexchange.com/questions/383552/measurementofoutputimpedanceofacmosinverter .PARAM V_SUPPLY = 3.3 .PARAM V_OUT = 2 *.PARAM INP_FREQ = '#INP_FREQ#' *.PARAM INP_PERIOD = '1/INP_FREQ' *.PARAM NO_PERIODS = '4' *.PARAM TMEAS_START = '(NO_PERIODS1)*INP_PERIOD' *.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD' .PARAM AC_POINTS = 10 .PARAM AC_START = 1000 .PARAM AC_STOP = 1E6 *** *** SUPPLY VOLTAGES *** *** VDD VDD 0 'V_SUPPLY' VSS VSS 0 0 *** *** INPUT SIGNAL *** *** ** VSIG IN VSS 0 ** VSIG IN VSS AC 1 DC 0 ** VSIG IN VSS AC 1 DC 'V_SUPPLY/2' *** *** CIRCUIT UNDER TEST *** *** MP OUT IN VDD VDD P1 W=2U L=2U MN OUT IN VSS VSS N1 W=1U L=2U ** CL OUT VSS 3p ** RIN IN VSS 1G CIN IN VSS 1 Rf OUT IN 1E15 ** Lf OUT IN 1E15 ** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214NoiseinCMOSInverter&p=1617292&viewfull=1#post1617292 *** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT *** *** ** this is a way to measure or plot the current source IOUT in spice using 0V voltage source VOUT OUT VOUT 0 *** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS IOUT VSS VOUT AC 1 *** *** ANALYSIS *** *** *.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP' *.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD' * *.PROBE TRAN V(IN) *.PROBE TRAN V(OUT) .OPTION POST PROBE ACCURATE .include modelcard.nmos .include modelcard.pmos ** https://github.com/imr/ngspice/blob/master/examples/xspice/table/modelcards/modelcard.nmos ** https://github.com/imr/ngspice/blob/master/examples/xspice/table/modelcards/modelcard.pmos .control *AC dec 'AC_POINTS' 'AC_START' 'AC_STOP' AC dec 10 1000 1E6 let ROUT=v(OUT)/abs(i(VOUT)) plot ROUT print ROUT > ROUT.log .endc .END

9th July 2018, 07:48 #17
 Join Date
 Jan 2008
 Location
 Bochum, Germany
 Posts
 44,233
 Helped
 13462 / 13462
 Points
 253,869
 Level
 100
Re: Problem measuring output impedance of CMOS inverter using ngspice
The test circuit should basically work. Rf may be a way too high if the MOSFETs show leakage current. 1e9 should be more than suffcient. Check the bias point!
1 members found this post helpful.

9th July 2018, 11:20 #18
 Join Date
 Feb 2016
 Posts
 503
 Helped
 1 / 1
 Points
 2,695
 Level
 12
Re: Problem measuring output impedance of CMOS inverter using ngspice
Rf may be a way too high if the MOSFETs show leakage current.
Check the bias point!

Advertisment

9th July 2018, 16:30 #19

9th July 2018, 17:11 #20
 Join Date
 Jan 2008
 Location
 Bochum, Germany
 Posts
 44,233
 Helped
 13462 / 13462
 Points
 253,869
 Level
 100
Re: Problem measuring output impedance of CMOS inverter using ngspice
... generates a (nearly) full feedback amplifier, i.e. gain≈1 for low frequencies (LF), with corresponding low LF output impedance.
Why if I decrease Rf from 1E15 to 1E9 , ROUT increases from 48.563 kohm to 48.5705 kohm
This is a selfbias CMOS inverter. Could you advise ?
+ Post New Thread
Please login