Synopsys: DC synthesis of design with different clocks

Hello all,

Greetings! Hope you all doing good!

I have a quick question about synopsys DC synthesis.

I have a top module called "topblock.v". This module has two sub modules called "block1.v", "block2.v".

The outputs of "block1.v" goes to "block2.v" as the inputs but the module "block1.v" is runnig with clock "clk_a" and the module "block2.v" is running with clock "clk_b".

Now the top module has two sub-modules running with two clocks!

I have a start up problem here.

1. Should I need to use TOPMODULE.v as design entry here? (TOPMODULE.v includes two submodules)?

2. I have used "set_clock groups" to seperate two clock group but I couldn't constraint the corresponding input,output delays.

3. Why I couldn't seperate inputs and outputs with respect to clocks?

4. I have the scripts below. Can anyone please let me know what is the problem with this script?

I also attached image to clarify the situation.

Thanks in advance.
Vivek.

Now if I remember my Tcl and the sdc commands correctly...

[get_ports CLK_A] will return CLK_A it won't return a collection of inputs that use CLK_A.

Therefore your command [remove_form_collection [all_inputs] [get_ports CLK_A]] does this...
[remove_from_collection {in1 in2 in3 in4} {clk_a}]
which leaves you with a collection of {in1 in2 in3 in4} and not what you expect: {in2 in3 in4}

You should be using [get_ports in1] if you want to remove the signal on CLK_B from the set. There might be a command to specify inputs that only go to CLK_B but it's not get_ports (maybe get_ports with some option? I really don't know)

ads-ee said:

Now if I remember my Tcl and the sdc commands correctly...

[get_ports CLK_A] will return CLK_A it won't return a collection of inputs that use CLK_A.

Therefore your command [remove_form_collection [all_inputs] [get_ports CLK_A]] does this...
[remove_from_collection {in1 in2 in3 in4} {clk_a}]
which leaves you with a collection of {in1 in2 in3 in4} and not what you expect: {in2 in3 in4}

You should be using [get_ports in1] if you want to remove the signal on CLK_B from the set. There might be a command to specify inputs that only go to CLK_B but it's not get_ports (maybe get_ports with some option? I really don't know)

Click to expand...

Hi,

Thanks for your quick reply!

Yeah, you are right! we can't use this command,
set_input_delay 1 -max -clock D_CLK [remove_from_collection [all_inputs] [get_ports CLK_A]]

But how to seperate inputs of specific clock from all_inputs???

As you mentioned we can specify the inputs seperately for the specfic clock but for the block having large number of inputs, writing all the inputs is painful isn't?

Also how to seperate outputs here? because the output is input to the another clock!!!

Thanks again for your reply.

set_input_delay or set_output_delay are only for pins of the device they don't apply to the block to block connections.

Personally I never used all_inputs or all_outputs, I specify using wildcards and partial names. This is where naming conventions really help.

e.g. Name all inputs on clk_a as ia_<some_input_pin_name> and all outputs as oa_<some_output_pin_name> now it's easy to specify all the pins for an output or input based on the clock domain.

ads-ee said:

set_input_delay or set_output_delay are only for pins of the device they don't apply to the block to block connections.

Personally I never used all_inputs or all_outputs, I specify using wildcards and partial names. This is where naming conventions really help.

e.g. Name all inputs on clk_a as ia_<some_input_pin_name> and all outputs as oa_<some_output_pin_name> now it's easy to specify all the pins for an output or input based on the clock domain.

Click to expand...

agreed, use wildcards and some naming strategy.