What is the correct way to write VHDL code for block using divided clock?

Lets say I am writing VHDL code for a block that at runtime in hardware can be controlled to use a divided version of the clock. This could be div by 2, div by 4, div by 8 or div by 16 e.g a SPI master in FPGA.

I think that in theory, the following methods exist:
1. Use PLL with clock multiplexer to select one clock to drive the design.
2. Use gated clock with the gating signal coming from a counter.
3. Use clock enable with the enable signal coming from a counter.

Are there any other ways? While one can write VHDL code that will do the above in simulation, when it comes to creating an actual design, we need to be aware of how to do this correctly with the FPGA technology we are using since it will have some special primitives, IP, directives to the tool e.t.c to make the above happen.

Does anyone know how to correctly design hardware using VHDL or whatever is actually required, that effectively uses a divided version of the clock signal in Altera and Xilinx designs?

Since your clocks are all divided by powers of two, a counter is the simplest approach. Your actual design will dictate the switch-over mechanism you use. Programmable counter, multiplexer, clock enable are all valid approaches. Avoid gated clocks in FPGAs.

Hi,

generating the ENABLE signal with a couter is the preferred solution.

Klaus

1. Seems a little over complicated, especially as the clocks are 2^n.
2. Never gate a clock in an FPGA
3. Usually the easiest solution. Probably most obvious for other readers too.

Usually we write a process like this:

process(clk)
begin
if rising_edge(clk) then
...
end if;
end process;

How should it be written to work with a divided clock that is being implemented using clock enable coming from a counter? I guess all the processes in the entire hierarchy of the design block using the divided clock, shall have all its clocked processes written following the same pattern and shall all input the clock enable signal, down the lowest level of hierarchy. It is here that I am getting confused, what is the proper way of writing this hmmmmmmm

I assume that the clock enable shall be asserted when the count reaches 1, 3, 7 e.t.c for clock division by 2, 4, 8 e.t.c.respectively?

Something like this:

process(clk)
begin
if rising_edge(clk) then
if enable='1' then
-- do your stuff here
end if;
end if;
end process;


In this case 'enable' signal is asserted for one clock cycle by your external counter every 2,3,4,5,6,7,..-th cycle of the clock.

I think a fourth way would involve creating a clock signal from a comparison. This would be the worst choice possible.

modern FPGAs have PLLs that have multiple outputs. Something like this would be good if large portions of the design are driven from the same clock enable.

using clock enable inputs is pretty common in FPGA designs. The only real issues are if you need to define multi-cycle paths for performance, or if you mix clock-enabled and non-clock-enabled logic.

I would approach the problem from a hardware perspective.
- does the involved FPGA core register provide a dedicated clock enable input?
- is the SPI operated at a frequency where logic core speed matters

Without dedicated clock enable, a mux between d and q must be used. Besides occupying LUT resources, it reduces maximum speed.


If the SPI clock is relative low (e.g. <= some 10 MHz), clock enable can be used without problems and is the preferred solution.