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File as a parameter for VHDL function

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filip.amator

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I have got several text files with data (lets say packet to be send over uart) and I want to send in order that data over uart from my process:

Code:
proc_stim : process

function send_packet(....)
...
end function send_packet;

begin

send_packet(..."packet1.txt"...);
wait for 10 us;
send_packet(..."packet2.txt"...);
wait for 10 us;
send_packet(..."packet3.txt"...);

wait;

end process proc_stim;

I need to declare a function and pass as a parameter a filename. Is this possible in VHDL? It seems that a file can be assigned to the variable of type "file" only during declaration and text file is linked to the variable for whole simulation (Iam using ModelSim and Questa)
 

Hi,

this usually is not a job for hardware .. it´s more a job for software.
Did you implement a processor core?

Klaus
 

Hi,

Sorry I forgot to mention - it is a testbench. The real hardware makes some problems and I want to check in my simulation what is wrong. LabView testing software saved all packets to text files and now I want to send to my UUT the same data. Basically I am looking a convenient way to open numerous text files, read values and pass into fifo.
 

Do you want to pass a file into a function, or a filename? they are two different things, and both possible. But if you want to drive a bus, you'll probably want a procedure instead
VHDL has a FILE_OPEN procedure you can call in the function, or procedure, but if you're passing in a filename then theres no need.

Below is an example:


Code VHDL - [expand]
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procedure send_packet(constant fname : in string;
                                
                     -- interface to drive
                     signal clk     : in  std_logic;
                     signal drive   : out std_logic_vector(31 downto 0) ) is
                     
  file pkt_file : text open read_mode is fname
  variable l    : line;
  variable d    : std_logic_vector(drive'range);
begin
  while not ENDFILE(pkt_file) loop
    readline(pkt_file, l);
    read(l, d);
    
    drive <= d;
    wait until rising_edge(clk);
  end loop;
  
end procedure send_packet;



Of course, this can get much, much more complicated.
The above code requires you use VHDL 2008 for standard libraries, otherwise you'll need to include the non-standard ieee.std_logic_textio (included with all simulators afaik) if you're running VHDL '93.

so in your testbench, you just write:


Code VHDL - [expand]
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process
begin
  send_packet("packet1.txt", clk, d);
  wait for 10 us;
  send_packet("packet2.txt", clk, d);
  wait for 10 us;
  send_packet("packet3.txt", clk, d);
  wait;
end process;

 

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