filip.amator
Full Member level 3
I have got several text files with data (lets say packet to be send over uart) and I want to send in order that data over uart from my process:
I need to declare a function and pass as a parameter a filename. Is this possible in VHDL? It seems that a file can be assigned to the variable of type "file" only during declaration and text file is linked to the variable for whole simulation (Iam using ModelSim and Questa)
Code:
proc_stim : process
function send_packet(....)
...
end function send_packet;
begin
send_packet(..."packet1.txt"...);
wait for 10 us;
send_packet(..."packet2.txt"...);
wait for 10 us;
send_packet(..."packet3.txt"...);
wait;
end process proc_stim;
I need to declare a function and pass as a parameter a filename. Is this possible in VHDL? It seems that a file can be assigned to the variable of type "file" only during declaration and text file is linked to the variable for whole simulation (Iam using ModelSim and Questa)