dzosgornik
Newbie level 5
Hello everyone,
I'm working with the Cyclone 10 GX and want to attach multiple modules to the EMIF (External Memory Interface) Controller. This controller has a reset output, which I would like to use as a global reset signal, since all modules are attached to the DRAM with their own DMAs. All modules operate with the EMIF clock (233.25 MHz) in order to minimize CDC logic (which is quite high for 128-bit data interfaces multiplied by 8 DMAs). When running timing analysis, I always get some problems with the Avalon Memory Interconnect, even after registering all waitrequest/read/write/etc. signals explicitly at DMA module boundaries. When digging deeper, there seems to be a problem with the EMIF reset output... Each of my modules uses solely asynchronous reset inputs (as far as I can tell from RTL analysis), so I'm not sure why this leads to timing problems. Do I need to set the reset output as false path?
Thanks in advance
I'm working with the Cyclone 10 GX and want to attach multiple modules to the EMIF (External Memory Interface) Controller. This controller has a reset output, which I would like to use as a global reset signal, since all modules are attached to the DRAM with their own DMAs. All modules operate with the EMIF clock (233.25 MHz) in order to minimize CDC logic (which is quite high for 128-bit data interfaces multiplied by 8 DMAs). When running timing analysis, I always get some problems with the Avalon Memory Interconnect, even after registering all waitrequest/read/write/etc. signals explicitly at DMA module boundaries. When digging deeper, there seems to be a problem with the EMIF reset output... Each of my modules uses solely asynchronous reset inputs (as far as I can tell from RTL analysis), so I'm not sure why this leads to timing problems. Do I need to set the reset output as false path?
Thanks in advance
