B21hasni
Junior Member level 3
how can I compile package and entity together,
the package is
the entity is
I have tried but I got this messege
Error (10481): VHDL Use Clause error at alu_test.vhd(3): design library "work" does not contain primary unit "ALU". Verify that the primary unit exists in the library and has been successfully compiled.
the package is
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package ALU is
function addition (A,B: std_logic_vector) return std_logic_vector;
function subtraction (A,B: std_logic_vector) return std_logic_vector;
function multiplication (A,B: std_logic_vector) return std_logic_vector;
function pass_A (A: std_logic_vector) return std_logic_vector;
function Logical_AND (A,B: std_logic_vector) return std_logic_vector;
function Logical_OR (A,B: std_logic_vector) return std_logic_vector;
function shift_R (A: std_logic_vector) return std_logic_vector;
function shift_L (A: std_logic_vector) return std_logic_vector;
end ALU;
package body ALU is
function addition (A,B: std_logic_vector) return std_logic_vector is
variable Y: std_logic_vector (15 downto 0);
begin
Y := A+B;
return Y;
end function;
function subtraction (A,B: std_logic_vector) return std_logic_vector is
variable Y: std_logic_vector (15 downto 0);
begin
Y := A-B;
return Y;
end function;
function multiplication (A,B: std_logic_vector) return std_logic_vector is
variable Y: std_logic_vector (31 downto 0);
begin
Y := A*B;
return Y;
end function;
function pass_A (A: std_logic_vector) return std_logic_vector is
variable Y: std_logic_vector (15 downto 0);
begin
Y := A;
return Y;
end function;
function Logical_AND (A,B: std_logic_vector) return std_logic_vector is
variable Y: std_logic_vector (15 downto 0);
begin
Y := A AND B;
return Y;
end function;
function Logical_OR (A,B: std_logic_vector) return std_logic_vector is
variable Y: std_logic_vector (15 downto 0);
begin
Y := A OR B;
return Y;
end function;
function shift_R (A: std_logic_vector) return std_logic_vector is
variable Y: std_logic_vector (15 downto 0);
begin
Y := '0'& Y(15 downto 1);
return Y;
end function;
function shift_L (A: std_logic_vector) return std_logic_vector is
variable Y: std_logic_vector (15 downto 0);
begin
Y := Y(14 downto 0)&'0';
return Y;
end function;
end package body;the entity is
Code:
library ieee;
use ieee.std_logic_1164.all;
use work.ALU.all;
entity ALU_test is
port(sel: in std_logic_vector(3 downto 0);
A,B: in std_logic_vector (15 downto 0);
Y: out std_logic_vector (31 downto 0));
end ALU_test;
architecture beh of ALU_test is
begin
process(sel,A,B)
begin
if sel = "0000" then
Y (15 downto 0) <= pass_A(A);
elsif sel="0001" then
Y (15 downto 0)<= Logical_AND (A,B);
elsif sel="0010" then
Y (15 downto 0) <= Logical_OR (A,B);
elsif sel="0011" then
Y (15 downto 0) <= addition (A,B);
elsif sel= "0100" then
Y (15 downto 0) <= subtraction (A,B);
elsif sel="0101" then
Y <= multiplication (A,B);
elsif sel= "0110" then
Y (15 downto 0) <= Shift_L (A);
elsif sel="0111" then
Y (15 downto 0)<= Shift_R (A);
end if;
end process;
end beh;I have tried but I got this messege
Error (10481): VHDL Use Clause error at alu_test.vhd(3): design library "work" does not contain primary unit "ALU". Verify that the primary unit exists in the library and has been successfully compiled.
