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Designing the output stage class ab

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bharath_k

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Hi everyone,

I need help in designing the following circuit. I designed M1, M2, M3, M4, M5, M6, M7 and M8 the normal way of designing two stage amplifier. I need help in designing M9, M10, M11 and M12. I was not given any specifications. I myself took the following specifications.

Gain=40-45db, GBW=50Mhz, Cload=10p, Iref=40u A.

Can anyone guide me how to go about selecting crossover current and completing the design. Any inputs will be very helpful. classabopamp.PNG
 

The cross-over current selection will be your final step about, your desired THD (Total Harmonic Distortion) will give you its value and if stability parameters are not too good those can update the current.
Share more specifications please (external feedback network, in/output voltage range, max. consumption, min/max supply voltage, etc.).
 

Hi, Sorry for the incomplete specifications. I am designing it for the first time and I do not have much idea about it. As I mentioned I do not have any specifications given and I am free to choose. I saw few papers and assuming the values.

1) I would like to implement a non-inverting amplifier.
2) ICMR (0.8-1.6).
3) VDD = 1.8, VSS = 0
4) output swing VDD-0.3, VSS-0.3

Unfortunately I am finding difficult to choose the values needed for the rest. Any typical values you can suggest me to choose.
 

1, non-inverting amplifier with gain>1 or a buffer? it matters, and both are non-inverting amp.
2, probably an NMOS input stage can handle this, it is fine.
3, ok
4, this is an issue. your class AB architecture's max output voltage is ~ VDD-(|Vdsat.5|+Vgs.11), where |Vdsat.5|+Vgs.11=|Vdsat.5|+Vdsat.11+Vth.nmos < 0.3V.
I don't know 22nm technology, but with good ~0.1V |Vdsat| for both NMOS and PMOS the max. Vth.nmos should be 0.1V. It is too small, even with sub-threshold operation for the output stage.
Check the Vth of your devices, if those are higher than 0.1-0.2V I think you cannot ensure your specifications.
...minimum output voltage has the same issue, figure out why.
 

Yeah that is the issue with this architecture that output swing is limited. So may be I can design for VDD-0.4 or VDD-0.45 and ?

and non-inverting with unity gain.
 

bharath_k said:
So may be I can design for VDD-0.4 or VDD-0.45 and ?
Click to expand...

Don't deal with me about the specifications please, it is a nonsense. I gave you a quite exact expression for the maximum output voltage. Figure out Vth of 22nm devices, put into the expression, calculate with at least 0.1V Vdsat and you will see what is the limit of this circuit.
 

I know Vth of the device and not sure whether I can share it. So gave the range. I have found out a way to design. Your inputs were very valuable :)
 

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