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Pipeline stages regs

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Alauddin123

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Hello All,

I came across the option of adding register pipeline stages(1,2,3) while generating the BRAM IP via coregen. can any one explain me in detail how this additional regs improve the performance of the core ?
 

It adds more registers, which may make it easier to route/fit the design to meet your timing requirements.
Improvements will be determined by many factors, including what the clock speed required is, how full the chip is, and what your design is.
 

Please read UG626 Synthesis and Simulation Design Guide and Chapter 5: Coding for FPGA Device Flow.
There is Pipelining section that describes why additional regs improve the performance.

The summary
Before pipelining:
01_Before_pipeline.png
The clock speed is limited by:
• Clock-to out-time of the source flip-flop
• Logic delay through four levels of logic
• Routing associated with the four function generators
• Setup time of the destination register

After pipelining:
02_After_pipeline.png
The clock speed is limited by:
• The clock-to-out time of the source flip-flop
• The logic delay through one level of logic: one routing delay
• The setup time of the destination register
In this example, the system clock runs much faster after pipelining than before pipelining.
 

In my understanding additional register stages for BRAMs are required if your instance requires lots of BRAM blocks and thus wiring to the processing logic would be spread across a wide range, requiring some pipeline registers to increase maximum operating frequency. In most cases you won't require these registers, as most use cases use - um... let's say max 10 BRAMs - for buffering and FIFOs and stuff. If you have a use case where you drive lots of BRAMs from a single module, then these registers will give you some performance benefits.
 

It depends on the clock frequency and where your BRAMs would be on the FPGA die.
It is possible to utilize a small number of BRAMs, but these BRAMs can be spread across whole FPGA die - then we could have also the timing issues.
If the synthesis tools ale trying hard to meet timing, you can help them by adding additional registers on critical paths.
Of course the cost of this is in increased latency.
 

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