Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Ref. design of S10 with a PCIe enabled 256-bit bursting slave interface (HPTXS) Port

Status
Not open for further replies.

hcu

Advanced Member level 4
Joined
Feb 28, 2017
Messages
101
Helped
0
Reputation
0
Reaction score
0
Trophy points
16
Activity points
874
Hello all,

please suggest me a reference design on stratix 10 board with a PCIe , enabled high performance burst interface (HPTXS) port of 256 bit width.
I searched on the net to have a clear understanding about this port, but not found anything. But, there are 2 paras of information available on the user-guide that available from the tool, but didn't understood.

someone please send me a link to understand the functionality of that port, referral design.


some questions
1. can i enable this HPTXS port irrespective of "enable DMA" option that is used to do dma transfers from host to fpga ?
2. once i enable this HPTXS port , i have to select - no. of pages and size of each page (on what basis should i select these two parameters) ?
3. how address mapping concept differs from maintaining descriptors table space, instantiating descriptor controller etc., (i think i asked 1 and 2 questions in otherway) ?

regards,
Anil
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top