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Verilog in Cadence Virtuoso

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ngox

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I've used Cadence Virtuoso for many years, but am somewhat new to Verilog or systemVerilog integration into this tool.

I've currently written a module sort of in this format (I've simplified it here):

Code:
module ABC (input x, output y);

XYZ I0 (.i(x), .o(y));

endmodule

module XYZ (input in, output out);

assign in = out;

endmodule

where module ABC is calling on module XYZ. From reading around, it seems like this would be the way to call another module, right? I've tried to place an equivalent symbol of ABC into a schematic along with some instances from analogLib and ahdlLib, and then specified the used formats using a config file. However, when I netlist and run using AMS as the simulator, it seems like nothing is happening. I don't get errors, but no waveforms are ever saved or plotted even though I've specified them in the Outputs section in ADE-L.

I feel like I'm missing something super obvious here, so any help would be greatly appreciated! I've tried reading a couple of tutorials online but still haven't been able to figure this out.
 

your "module XYZ" has errors, not sure if those are real or not as you've posted a "simplified" version.

Your instantiated version in ABC has i and o as the input and output port names respectively, but you have in and out in the XYZ port definitions.

You are assigning in which is defined as an input, not sure how this even compiled as it should have been an illegal assignment.

This is why posting unverified "testcase" code is a bad idea. One should always verify that testcase code compiles properly and exhibits the issue.
 

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