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[SOLVED] Separate local PWELL and PSUB to pass LVS softcheck

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quyleanh

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My layout has 6 termials NMOS: D, G, S, B, DNW_ISO, PSUB.
B is connected to VSS
DNW_ISO (deep nwell isolation) is connected to VDD
PSUB is connected to VSSPS

I can isolate the local PWELL (B termial) and the PSUB (PSUB) terminal by adding DNW.
Because the layout is standard cell so I cannot surround DNW layer by NWELL ring (which is should be done in that way). If I add NWELL ring, I will not abut with the other cell.

Because the DNW layer is not surrounded by NWELL ring, LVS check notify the Softcheck error, which is PWELL and PSUB is shorted.

Could anyone tell me how can I separate local PWELL and PSUB to pass LVS softcheck in this case? Thank you.
 

This is a common problem with DNW layouts. Option 1 is to wait to run LVS until you come to the level where the DNW is terminated. Option 2 is to temporarily terminate the DNW in the cell you are working on in order to get LVS clean. Option3 is to created a temporary cell, place the cell you are working on into it, terminate the DNW and run LVS.
 
rangermad said:
This is a common problem with DNW layouts. Option 1 is to wait to run LVS until you come to the level where the DNW is terminated. Option 2 is to temporarily terminate the DNW in the cell you are working on in order to get LVS clean. Option3 is to created a temporary cell, place the cell you are working on into it, terminate the DNW and run LVS.
Click to expand...

After all, I think option 1 is better. The NWell ring must be rounded DNW area.
Because they are standard cell, in the top level, I will correct this. Thank you.
 

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