carmeloA
Junior Member level 1
Hi to all,
I want to build a simple FSM in vhdl where the output is the same of the state encoding of the FSM.
I want this behaviour because I want to change the state encoding at every syntesis (with the command set_fsm_encoding in DC) and make some consideration.
For example, given a simple state machine:
In this example, the output is fixed 000 when state 1 etc; what i want instead, is that the signal "output" is always the state encoding that design vision gives to the fsm.
I'd like to ask if anyone could give me any tips to achive my goal.
Thank you so much
I want to build a simple FSM in vhdl where the output is the same of the state encoding of the FSM.
I want this behaviour because I want to change the state encoding at every syntesis (with the command set_fsm_encoding in DC) and make some consideration.
For example, given a simple state machine:
Code:
TYPE states IS (state1,state2 ... state8);
SIGNAL current_state, next_state : states;
BEGIN
current_state_update: process(clk, reset)
begin
if reset='1' then
current_state<=state1;
elsif (clk'event and clk='1') then
current_state<=next_state;
end if;
end process current_state_update;
next_state_up : process(current_state)
begin
case current_state is
when state1=> next_state<=state2;
when state2=> next_state<=state3;
....
when state8=> next_state<=state1;
end case;
end process next_state_up;
output_gen: process(current_state)
begin
case current_state is
when state1=> output<="000";
when state2=> output<="001";
....
when state8=> output<="111";
when others=> output<="000";
end case;
end process output_gen;In this example, the output is fixed 000 when state 1 etc; what i want instead, is that the signal "output" is always the state encoding that design vision gives to the fsm.
I'd like to ask if anyone could give me any tips to achive my goal.
Thank you so much