Memory delay in DDS signal generator

Hello!
I have a question about design in high frequency DDS genarators. It's about delay of a memory which contain lookup tables. I'm curious about how modern DDS signal generators deal with that delay of memory. I know that there are some adders/registers with can oparate at GHz's frequencies. But what about memory? I've found some, which have delay of 5-10ns, but that mean those are capable to deal with 200-100MHz clock speeds. So how these generators generate so high frequencies?

First thought I had, is that first the signals are generated and modulated in low frequency domain and then mixed with high GHz's signals. But is doing so won't distort these signals modulated with those fancy modulations(I/Q signals etc)? Or maybe I'm wrong and it won't?

I've build simple DDS using adder D-flipflops and a RAM memory (74ls83/74ls374 and AM21l48), but it can operate only at approx 50MHz clock freq. I'm just curious how it's done in those >4000$ vector GHz generators. It just bothers me so much

I would suspect the generators are using something like an FPGA and just have a handful of parallel LUTs. eg, based on parameters, you compute phase[n], phase[n+1], phase[n+2], ... Then you use multiple lookup tables along with any fancy compensation. You end up having multiple samples generated at 200MHz. Then you send these to a PISO that sends them to a DAC and output buffer.

Or the hetrodyning technique you mention could also be done possibly. Possibly there is some online calibration to correct for I/Q imbalance by some changes to DDS input phase and DDS output scale.

Sorry for late reply, but I was unable to get to PC.

Could you provide me maybe a schematic or something which shows how that parallel memory is realised? I've been looking at google but couldn't find anything. How to connect multiple memories to work as you've mentioned?

Do I undersood this correctly? You have for example 3 memories. Each of these contains n, n+1, n+2 sample number, respectively. So for 300MHz clock time each of these memories have to work at clock time of 100MHz. Then these samples are send to a PISO register which work at 300MHz clock.

Thanks in advance.

I believe any beginner in digital design can sketch a logic combining the output of multiple memory devices into a single data stream of n-fold speed. The interesting question is which suitable hardware you have available. Recent instruments are using FPGA to achieve up to many GHz data rates.

Well as I've mentioned I'm using 7400 ICs for now. I think FPGA is out of my range for now. I would like to build DDS capable of getting freqencies 0-100MHz. That's why I'm stuggled with that memory delay. When all of logic is done I plan to program maybe PIC or Atmega microcontroller. 7400 are for testing now. If I get to know how to solve that memory problem I will move to some higher frequency adders/registers.

100 MHz sounds moderate, there's a large portfolio of SRAM and SSRAM with < 10 ns cycle time. TTL or standard HC logic however can't handle 100 MHz, need 74S or recent fast CMOS family.

Logic that spans more than a few ICs can be implemented cheaper in a PLD these days.

Yeah I know about TTL's frequency. Ive seen that 74LVC can handle 250+MHz.
About PLD's I would have to buy development boards, learn to program it, etc. Too high cost for me now.

Thanks for help.

kamilkarp said:

Yeah I know about TTL's frequency. Ive seen that 74LVC can handle 250+MHz.
About PLD's I would have to buy development boards, learn to program it, etc. Too high cost for me now.

Thanks for help.

Click to expand...

HUH????? You want to build a DDS from scratch but PLDs are too complicated for you? You're going to build a DDS out of discretes? A development board would cost you a lot less than a whole bunch of RAMS plus the cost of psychiatric care you're going to need after you try and get that thing to work.

Furthermore, putting in some effort to learn about PLD/FPGAs would be a good investment.

About PLD's I would have to buy development boards, learn to program it, etc. Too high cost for me now.

Click to expand...

Major companies are giving away their educational boards for a price that hardly covers the logic device costs. The real "cost" is in learning, a good investment I believe.

I had to design discrete logic in the 70th and 80th when no PLD except for small PAL and GAL have been affordable or even available. Clock speeds above 50 MHz hardly achievable. Logic design has become so easy now.

Hi,

Logic design has become so easy now.

Click to expand...

Yes.
Especially finding mistakes and correct them..
With PLDs you have simulators and you may test everything. To debug the system you may add additional logic without cost....and immediately get the result.
No need to replace wires and no need for annoying soldering... just program the corrected code into the PLD.

Many software tools are free to use. And there are really cheap develeopment boards.

Maybe you can persuade a distributor to get an even better price.

Klaus

kamilkarp said:

Yeah I know about TTL's frequency. Ive seen that 74LVC can handle 250+MHz.
About PLD's I would have to buy development boards, learn to program it, etc. Too high cost for me now.

Thanks for help.

Click to expand...

In fact you can do whole design and simulations of your DDS in the software. Free version of ModelSim allows you to simulate VHDL/Verilog design and later do the gate level simulation and verify if timings are OK. Making a DDS from a bunch of TTL isn't a brightest idea. Learning is for free in that case and any knowledge gained is far more valuable than soldering TTLs.

Maybe think about CPLDs (cheaper then FPGA), e.g.

Maybe in later time I'll give FPGA a try, but for now I think I will stick to 74's. That DDS idea is only "for fun" so I'm not talking about I don't know big bit depth/resolution of this generator that's why cost of the 74 ICs won't be high because I won't need it much.

About FPGA only I knew was that it exists. Wasn't deep learning about it. That's why I don't know much about it. Programming it is done in C/asm same way as microcontrollers?

kamilkarp said:

Maybe in later time I'll give FPGA a try, but for now I think I will stick to 74's.

Click to expand...

Bad choice...74's are nearly obsolete in modern designs. FPGAs are used across many designs.

kamilkarp said:

About FPGA only I knew was that it exists. Wasn't deep learning about it. That's why I don't know much about it. Programming it is done in C/asm same way as microcontrollers?

Click to expand...

FPGA is not programmed like a microprocessor/microcontroller, it is done using logic design techniques.

Entry methods include:
1. You can draw schematics with primitives like flip-flops, multiplexers, decoders, gates, etc.
2. Or you can design at a higher abstraction level using VHDL/Verilog (both hardware description languages, not general purpose programming languages).
3. If you have lots of money you can buy a $20K+ tool and learn how to write C that can be compiled into VHDL/Verilog that can then be synthesized and implemented on an FPGA. But then you've already indicated you aren't loaded with cash.
4. Matlab/Simulink ($) and the appropriate vendor tools (more $).

Out of the four methods I would recommend 2 as the most expedient and cost effective solution as you can download the free versions of vendor tools from Xilinx/Altera(Intel), which includes a simulator. This means you can design the DDS in VHDL/Verilog and run simulations on the design to debug and verify the functionality. Then if you so choose to see it working on hardware, you can implement it for a target board that can be a CPLD or FPGA from inexpensive to expensive (whatever you budget dictates).

kamilkarp said:

Sorry for late reply, but I was unable to get to PC.

Could you provide me maybe a schematic or something which shows how that parallel memory is realised? I've been looking at google but couldn't find anything. How to connect multiple memories to work as you've mentioned?

Do I undersood this correctly? You have for example 3 memories. Each of these contains n, n+1, n+2 sample number, respectively. So for 300MHz clock time each of these memories have to work at clock time of 100MHz. Then these samples are send to a PISO register which work at 300MHz clock.

Thanks in advance.

Click to expand...

Sure. In my case I was thinking more like 8-12 tables with dual lookups and a post-processing stage. The main point is that you can have a lot of pipelining and parallel processing. Every part of the DDS can be pipelined -- even the accumulator!

Programming FPGA's is done using VHDL/Verilog for the most part. These are hardware description languages. The emphasis on "description of hardware". C/ASM describes a sequence of operations. HDL describes HW -- perhaps even a CPU.