Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Clock slew and data slew

Status
Not open for further replies.

sjt1003

Newbie
Joined
Jun 21, 2018
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
11
I am having some scripts for running a physical design flow. There I am having a script where limit for clock slew and data slew is defined.

Clock slew value is 0.200 ns
Data slew value is 0.400 ns

So my query is why do we have clock slew limit lesser than the data slew limit ? Does clock buffers have any roll in this?
 

It seems like a basit nyquist criterion for data sampling, probably to avoid data sampling before clock slew is satisfied.

What is your specifications?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top