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Hspicerf trannoise setup for PLL simulation

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tim82518

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hey man

I am a beginner of PLL design. Here I have a problem about how to setup the .trannoise parameters to measure the jitter. Would anyone share your experience about the setup of trannoise? Thank you very much.

My PLL design has 200MHz output frequency. Following the format in hspice manual showing below, I'm curious about how to determine the value of "seed", "SCALE", "FMIN" and "FMAX".
About the FMAX, I have noticed that the manual suggest to 2*highest frequency of circuit. Why is that?

2018-06-21.png

BR
CH
 

tim82518 said:
I'm curious about how to determine the value of "seed", "SCALE", "FMIN" and "FMAX".
Click to expand...
You don't have to set "seed" and "SCALE".

If you don't specify "FMIN", "FMIN" is setted to "FMAX".
So if you would like to include low frequecy noise more accurately, set "FMIN"

tim82518 said:
About the FMAX, I have noticed that the manual suggest to 2*highest frequency of circuit.
Why is that?
Click to expand...
Basic Sampling Theory.
 
Hi!

Thanks for your reply
Here I have a DAC with 6MHz frequency clock. The band-of-interest is about 100kHz.
In this case, should FMAX be set to 12MHz or 200kHz ???
Furthermore, what is the physical meaning of "seed" ???
Thanks!

BR
CH
 

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