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[SOLVED] Common POLY layer in the digital standard cells

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Hi all!
I have a question related with the standard cell layout.
I have revised 28nm digital stdcells layout obtained from foundry and I am little bit confused - in this cells POLY layers (gates of MOS) are connected together in the upped and bottom parts of the cell (looks same as in the attached picture for the CMOS inverter).
Why they are connected together?
inv.jpeg
 

Picture is not representative of the true layout. You wouldn't have horizontal poly like that.
 

I cannot show real layout due to NDA. In real layout I can see wide (much wider then gate POLY) POLY layer in the upper and bottom parts of the cell - exactly as in the picture. Any ideas?
I have checked in ICC - this is POLY layer.
 

Horizontal polygons of POLY have different datatype in the GDS file. It is marker layer "Cut-POLY".
 
Thank you for your answer!
Can you, please, elaborate why do we need this "cut-POLY" layer?
 

Guys, please, cut poly is not poly. It is effectively a CUT on the poly layer.
 

But what this CUT layer do with POLY layer, if it will be assigned to the POLY layer?
Cut it during manufacture of the chip?
 

It is not the same layer. Look at the GDS/layout carefully.

CUTPoly was introduced in newer nodes because poly became gridded and regular for DFM reasons. Yet you still need to separate transistors from each other, so you need a way to cut the poly grid. You do that with the CUTPoly layer. It is horizontal, yes, but it is not a horizontal poly layer.
 
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