aletar
Newbie level 3
Hello
My project has to operate with both negative (-1.2V) and high (+6V) voltages.
For this I am using high voltage transistors from the TSMC065 library (nch_hv25). They differ from regular transistors by a special layer called HVD on the drain.
I am trying to put a DNW under these transistors so I can use negative voltage for the bulk.
Without the DNW LVS (Calibre) passes without problems but when I add the DNW it recognizes the transistors in the layout as NCH_25_DNW and says they are different from the ones in the schematic.
(Assura crashes saying there are unbound devices probably for the same reason)
There is no cell in the library that has both the HVD layer and a DNW.
I thought of a couple of ways to solve this issue:
1. Somehow make the LVS recognize the transistor correctly (with filters of name binding or some other way)
2. Create a new cell with the transistor I need (HVD and DNW). If I do, how to make the LVS recognize it as a single useparable unit?
3. Change the transistors in the schematic to NCH_25_DNW and add the HVD layer manually. Will this affect the transistor performance?
Questions:
1. Why isn't there a cell with HVD and DNW? Is it because it won't work or just nobody ever uses it?
2. What is the best way to solve this issue? How would you implement it? (I'm a beginner in virtuoso and IC design in general)
3. Are there other issues you expect to come up because of the combination of high and negative voltages?
My project has to operate with both negative (-1.2V) and high (+6V) voltages.
For this I am using high voltage transistors from the TSMC065 library (nch_hv25). They differ from regular transistors by a special layer called HVD on the drain.
I am trying to put a DNW under these transistors so I can use negative voltage for the bulk.
Without the DNW LVS (Calibre) passes without problems but when I add the DNW it recognizes the transistors in the layout as NCH_25_DNW and says they are different from the ones in the schematic.
(Assura crashes saying there are unbound devices probably for the same reason)
There is no cell in the library that has both the HVD layer and a DNW.
I thought of a couple of ways to solve this issue:
1. Somehow make the LVS recognize the transistor correctly (with filters of name binding or some other way)
2. Create a new cell with the transistor I need (HVD and DNW). If I do, how to make the LVS recognize it as a single useparable unit?
3. Change the transistors in the schematic to NCH_25_DNW and add the HVD layer manually. Will this affect the transistor performance?
Questions:
1. Why isn't there a cell with HVD and DNW? Is it because it won't work or just nobody ever uses it?
2. What is the best way to solve this issue? How would you implement it? (I'm a beginner in virtuoso and IC design in general)
3. Are there other issues you expect to come up because of the combination of high and negative voltages?
