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Folded cascode OTA design

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Shishira

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Hi all,
I am trying to design FC-OTA (single ended o/p), I was not given any specifications so I made one referring few papers.
Specs:
vdd = 1.8V (by technology)
vthn/p = +200mv/ - 210mv
Kn = 200µA/V² Kp = 60µA/V²
SR= 20V/µs
cL = 500fF
gbw = 100Mhz
ICMR = 0.6 to 1.6 (nmos diff pair)
o/p swing = 0.3 to 1.5
gain = 55 db.
Q1] Are these specifications reasonable to start a design?
Q2] I followed steps from Allen holberg and designed the schematic as per above specs. But, my pmos current cources M4 & M5(above nmos diff pair) & its bias transistor are in triode region. **broken link removed**All other transistors are in region 2.
Q3]My circuit is giving gain of 60 db and gbw = 40 Mhz, why is there a huge drop in gbw.
 

Q1) Yes, sort of. If you do the sanity checks on the numbers, you can get to some educated guess:

Slew rate gives you current: A 20V/us SR and a 500-fF load implies a minimum current of I > 2e8*0.5e-12 = 10 uA (which is very small.)

gbw = 100 MHz = 600 Mrads = gm/C => 300 uS => W/L ~ 100, which is reasonable, etc.

Q2) Attachment seems broken, but change the bias voltage accordingly?

Q3) The triode transistors could be a reason. Did you use wug or fug? 2pi was there or not? A factor 2 is not necessarily a huge drop. Try increase the current two times to see if you improve the result. Gm has to be increased.
 

jjx said:
Q1) Yes, sort of. If you do the sanity checks on the numbers, you can get to some educated guess:

Slew rate gives you current: A 20V/us SR and a 500-fF load implies a minimum current of I > 2e8*0.5e-12 = 10 uA (which is very small.)

gbw = 100 MHz = 600 Mrads = gm/C => 300 uS => W/L ~ 100, which is reasonable, etc.

Q2) Attachment seems broken, but change the bias voltage accordingly?

Q3) The triode transistors could be a reason. Did you use wug or fug? 2pi was there or not? A factor 2 is not necessarily a huge drop. Try increase the current two times to see if you improve the result. Gm has to be increased.
Click to expand...

Q2] I am using transistor to generate bias voltage to M4 and M5. Any suggestion to understand how to generate bias voltages?
I read few literature, but not confident about it.
Q3] I did use 2pi for calculations. yeah, the triode transistors may be the reason .
 

I think a picture would simplify, it's hard otherwise to know what M4 and M5 are. Nevertheless, biasing those should not really be complicated. Do you have the correct mirror ratios?
 

fc_ota.JPG

Hi, Please find the attachment. The current ratio required is 1.5:1 i.e 25uA current in P3 and 37.5uA in P4 and P2.

I repeated the calculations with Itail 25uA and optimized little after simulations.
Now I solved the saturation issue of pmos current sources (P2 and P4 in attachment). But its biasing transistor P3 is still in triode region.

P2=P4=P5=P6= 40u/500n
n0=n1= 25u/500n
n6=n8=n10=n11=7u/500n
n2=n3=n4=n5=5.5u/1u [increased length to have better psrr]
p3=27u/500n( biasing for P2 and P4)
p1=1.5u/500n

Are these ratios reasonable to further analyze op amp parameters?
 

You connected all PMOS bulks to gnd. Source-Bulk junctions are forward biased, this is not normal operation. Connect PMOS bulks to vdd.
 

Hi, thanks for the comment. I am working on special transistor from global foundries. It's a small part of their research on their latest technology.
So in this case, it's 'back gate'. I have been strictly instructed to connect all back gates to gnd irrespective of nmos n pmos.
But, I have been facing issues in approximating the Vth of pmos due to this back gate effect.
It's coming +ve, which is too weird.
 

frankrose said:
You connected all PMOS bulks to gnd. Source-Bulk junctions are forward biased, this is not normal operation. Connect PMOS bulks to vdd.
Click to expand...
For this FDSOI technology back-gate default connection is ground for all core devices (however for thick oxide ones not).

@Shishira: How do you check the region of operation of transistors?
If I recognizing the process correctly, some of the dcOP parameters are calculated in wrong way (with default ADE options) and you should not believe them. Check if gm/gds is greater than 1.
 
Yes you are right about core devices, but I was told to connect all bulk to gnd for thick oxide ones as well .
So what's the best way to calculate dcOP parameters for this technology?
vth for pmos is also bit confusing, even in plots.
 

Threshold voltage is a non-physical parameter so you should not worry about it, but base all necessary calculations on inversion coefficient.
About a Vth, in pdk documentation should be a hint, what should be set to achieve a proper results.
 

Dominik Przyborowski said:
Threshold voltage is a non-physical parameter so you should not worry about it, but base all necessary calculations on inversion coefficient.
About a Vth, in pdk documentation should be a hint, what should be set to achieve a proper results.
Click to expand...
Could you tell me what is inversion coefficient that should be used for calculation ?
The pdk documentation is the " .scs " file of that transistor??
 

*.scs are the Spectre® model files
in PDK's main directory should be a 'doc' directory with tones of pdf files consisting tutorials, manuals, model descriptions and a lot of other stuff.

Informations on inversion coefficient can easily be found both in google like in the textbooks (i.e Enz, Vittoz; Binkley; Jespers). On this forum exists a number of threads touching this topic also.
 

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