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[HSpice] Invertor Simulation Problem

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EEPuppyPuppy

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I am trying to simulate an invertor by using this model. However, the output is very wired like the plot below.
untitled.jpg
It does not show the invertor property at all. Also, I have no idea that why the output can even go above the voltage supply.
Could anyone help me? Thank you so much.

Code: 
*Single invertor circuit
.LIB '/home/icsrl/TECHNOLOGY/FROM_MOSIS/TSMC/65nm/PDK/CRN65GP/models/hspice/crn65gplus_2d5_lk_v1d0.l' TT

vdd 3 0 DC 1V
vin 1 0 PULSE (0 1 0n 1n 1n 0.1n 2.2n)

*Schimitt trigger circuit
mp1 2 1 3 3 pch L=15u W=60u  
mn1 2 1 0 0 nch L=15u W=15u

cout 2 0 0.1pf

.TRAN 0.01ns 10ns
.option post=1 
.END
 
Last edited:

To invert a signal, the P device must be uppermost. The N device must be at bottom.
Your plot looks as though their positions are reversed, so that they act like emitter followers.
 

BradtheRad said:
To invert a signal, the P device must be uppermost. The N device must be at bottom.
Your plot looks as though their positions are reversed, so that they act like emitter followers.
Click to expand...

Thanks for your response. The PMOS is actually at the top which connected to Vdd and the NMOS is at bottom connected to the ground.
 

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